Added Fmax test projects for Quartus and for Vivado

Author: pConst

example_projects/quartus_fmax_test_prj_template_v3/.gitignore

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+#------------------------------------------------------------------------------
+# .gitignore for Intel Quartus
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# INFO ------------------------------------------------------------------------
+# rename the file to ".gitignore" and place into your Quartus project directory
+#
+
+
+# junk files
+*.qws
+*_assignment_defaults.qdf
+c5_pin_model_dump.txt
+*.ipregen.rpt
+*_summary.csv
+*_early_pwr.csv
+
+# junk directories
+/.qsys_edit
+/db
+/incremental_db
+/greybox_tmp
+
+# design space explorer
+/dse
+dse1_base.qpf
+dse1_base.qsf
+*.dse.rpt
+*.archive.rpt
+
+/out
+

example_projects/quartus_fmax_test_prj_template_v3/clean_quartus.bat

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+@echo off
+rem ------------------------------------------------------------------------------
+rem  clean_quartus.bat
+rem  Konstantin Pavlov, pavlovconst@gmail.com
+rem ------------------------------------------------------------------------------
+
+rem   Use this file as a boilerplate for your custom clean script
+rem   for Quartus projects
+
+SET PROJ=test
+
+rem Common junk files
+del /s /q .\%PROJ%.qws
+del /s /q .\c5_pin_model_dump.txt
+del /s /q .\%PROJ%.ipregen.rpt
+del /s /f /q .\.qsys_edit\*
+rmdir /s /q .\.qsys_edit\
+del /s /q .\%PROJ%_assignment_defaults.qdf
+
+rem Compilation databases
+del /s /f /q .\db\*
+rmdir /s /q .\db\
+del /s /f /q .\incremental_db\*
+rmdir /s /q .\incremental_db\
+del /s /f /q .\greybox_tmp\*
+rmdir /s /q .\greybox_tmp\
+
+rem Output directory
+del /s /f /q .\out\*
+rmdir /s /q .\out\
+
+rem Design space explorer files
+del /s /f /q .\dse\*
+rmdir /s /q .\dse\
+del /s /q .\dse1_base.qpf
+del /s /q .\dse1_base.qsf
+del /s /q .\%PROJ%.dse.rpt
+del /s /q .\%PROJ%.archive.rpt
+
+rem Early power estimator files
+del /s /q .\%PROJ%_early_pwr.csv
+
+pause
+goto :eof

example_projects/quartus_fmax_test_prj_template_v3/src/clk_divider.sv

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+//------------------------------------------------------------------------------
+// clk_divider.sv
+// published as part of https://github.com/pConst/basic_verilog
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+// INFO ------------------------------------------------------------------------
+//  Divides main clock to get derivative slower synchronous clocks
+//
+
+/* --- INSTANTIATION TEMPLATE BEGIN ---
+
+clk_divider #(
+  .WIDTH( 32 )
+) CD1 (
+  .clk( clk ),
+  .nrst( 1'b1 ),
+  .ena( 1'b1 ),
+  .out(  )
+);
+
+--- INSTANTIATION TEMPLATE END ---*/
+
+
+module clk_divider #( parameter
+  WIDTH = 32
+)(
+  input clk,
+  input nrst,
+  input ena,
+  output logic [(WIDTH-1):0] out = '0
+);
+
+
+always_ff @(posedge clk) begin
+  if ( ~nrst ) begin
+    out[(WIDTH-1):0] <= '0;
+  end else if (ena) begin
+    out[(WIDTH-1):0] <= out[(WIDTH-1):0] + 1'b1;
+  end
+end
+
+endmodule

example_projects/quartus_fmax_test_prj_template_v3/src/main.sdc

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+
+# main reference clock, 500 MHz
+create_clock -period 2.000 -waveform { 0.000 1.000 } [get_ports {clk}]
+
+derive_pll_clocks
+derive_clock_uncertainty

example_projects/quartus_fmax_test_prj_template_v3/src/main.sv

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+//------------------------------------------------------------------------------
+// main.sv
+// published as part of https://github.com/pConst/basic_verilog
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+// INFO ------------------------------------------------------------------------
+// minimal FMAX test project template, v3
+//
+// - use this as a boilerplate for fast prototyping and FMAX investigating
+// - inputs and outputs are registered to allow valid timequest output
+//   even if your custom logic/IPs have combinational outputs
+// - SDC constraint file assigns clk to 500MHz to force fitter to synthesize
+//   the fastest possible circuit
+//
+
+`define WIDTH 64
+
+module main(
+
+  input clk,
+  input nrst,
+
+  input [`WIDTH-1:0] in_data,
+  output logic [`WIDTH-1:0] out_data
+);
+
+// input registers
+logic [`WIDTH-1:0] in_data_reg = '0;
+always_ff @(posedge clk) begin
+  if( ~nrst ) begin
+    in_data_reg[`WIDTH-1:0] <= '0;
+  end else begin
+    in_data_reg[`WIDTH-1:0] <= in_data;
+  end
+end
+
+logic [`WIDTH-1:0] out_data_comb = '0;
+
+// place your test logic here ==================================================
+
+logic [31:0] div_clk;
+clk_divider #(
+  .WIDTH( 32 )
+) cd1 (
+  .clk( clk ),
+  .nrst( nrst ),
+  .ena( 1'b1 ),
+  .out( div_clk[31:0] )
+);
+
+always_comb begin
+  out_data_comb[`WIDTH-1:0] <= in_data_reg[`WIDTH-1:0] ^ div_clk[31:0];
+end
+
+
+// =============================================================================
+
+// output registers
+always_ff @(posedge clk) begin
+  if( ~nrst ) begin
+    out_data[`WIDTH-1:0] <= '0;
+  end else begin
+    out_data[`WIDTH-1:0] <= out_data_comb[`WIDTH-1:0];
+  end
+end
+
+endmodule

example_projects/quartus_fmax_test_prj_template_v3/test.qpf

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+PROJECT_REVISION = "test"

example_projects/quartus_fmax_test_prj_template_v3/test.qsf

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+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CGXFC4C7F27C8
+set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition"
+
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY out
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name TOP_LEVEL_ENTITY main
+
+
+set_global_assignment -name SYSTEMVERILOG_FILE ./src/main.sv
+set_global_assignment -name SYSTEMVERILOG_FILE ./src/clk_divider.sv
+set_global_assignment -name SDC_FILE ./src/main.sdc
+
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

example_projects/quartus_test_prj_template_v4.7z

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+
+
+*.cache
+*.hw
+*.runs
+*.sim
+.Xil
+
+*.jou
+*.log
+

example_projects/vivado_fmax_test_prj_template_v3/.gitignore

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+@echo off
+rem ------------------------------------------------------------------------------
+rem  clean.bat
+rem  Konstantin Pavlov, pavlovconst@gmail.com
+rem ------------------------------------------------------------------------------
+
+rem Use this file as a boilerplate for your custom clean script
+rem for Vivado/Vitis projects
+
+SET PROJ=test
+
+del /s /f /q .\%PROJ%.cache\*
+rmdir /s /q .\%PROJ%.cache\
+
+del /s /f /q .\%PROJ%.hw\*
+rmdir /s /q .\%PROJ%.hw\
+
+del /s /f /q .\%PROJ%.runs\*
+rmdir /s /q .\%PROJ%.runs\
+
+del /s /f /q .\%PROJ%.sim\*
+rmdir /s /q .\%PROJ%.sim\
+
+del /s /f /q .\.Xil\*
+rmdir /s /q .\.Xil\
+
+del /s /f /q .\*.jou
+del /s /f /q .\*.log
+
+pause
+exit