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Updated testbench template
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example_projects/testbench_template_tb/main_tb.sv

Lines changed: 75 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,15 @@
1414

1515
module main_tb();
1616

17+
initial begin
18+
// Print out time markers in nanoseconds
19+
// Example: $display("[T=%0t] start=%d", $realtime, start);
20+
$timeformat(-9, 3, " ns");
21+
22+
// seed value setting is intentionally manual to achieve repeatability between sim runs
23+
$urandom( 1 ); // SEED value
24+
end
25+
1726
logic clk200;
1827
sim_clk_gen #(
1928
.FREQ( 200_000_000 ), // in Hz
@@ -26,6 +35,28 @@ sim_clk_gen #(
2635
.clkd( )
2736
);
2837

38+
logic nrst_once;
39+
40+
logic [31:0] clk200_div;
41+
clk_divider #(
42+
.WIDTH( 32 )
43+
) cd1 (
44+
.clk( clk200 ),
45+
.nrst( nrst_once ),
46+
.ena( 1'b1 ),
47+
.out( clk200_div[31:0] )
48+
);
49+
50+
logic [31:0] clk200_div_rise;
51+
edge_detect ed1[31:0] (
52+
.clk( {32{clk200}} ),
53+
.anrst( {32{nrst_once}} ),
54+
.in( clk200_div[31:0] ),
55+
.rising( clk200_div_rise[31:0] ),
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.falling( ),
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.both( )
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);
59+
2960
// external device "asynchronous" clock
3061
logic clk33;
3162
logic clk33d;
@@ -40,70 +71,72 @@ sim_clk_gen #(
4071
.clkd( clk33d )
4172
);
4273

74+
4375
logic rst;
4476
initial begin
45-
#0 rst = 1'b0;
46-
#10.2 rst = 1'b1;
47-
#5 rst = 1'b0;
48-
//#10000;
77+
rst = 1'b0; // initialization
78+
repeat( 1 ) @(posedge clk200);
79+
4980
forever begin
50-
#9985 rst = ~rst;
51-
#5 rst = ~rst;
81+
repeat( 1 ) @(posedge clk200); // synchronous rise
82+
rst = 1'b1;
83+
//$urandom( 1 ); // uncomment to get the same random pattern EVERY nrst
84+
85+
repeat( 2 ) @(posedge clk200); // synchronous fall, controls rst pulse width
86+
rst = 1'b0;
87+
88+
repeat( 100 ) @(posedge clk200); // controls test body width
5289
end
5390
end
54-
5591
logic nrst;
5692
assign nrst = ~rst;
5793

94+
5895
logic rst_once;
5996
initial begin
60-
#0 rst_once = 1'b0;
61-
#10.2 rst_once = 1'b1;
62-
#5 rst_once = 1'b0;
63-
end
97+
rst_once = 1'b0; // initialization
98+
repeat( 1 ) @(posedge clk200);
6499

65-
logic nrst_once;
66-
assign nrst_once = ~rst_once;
100+
repeat( 1 ) @(posedge clk200); // synchronous rise
101+
rst_once = 1'b1;
67102

68-
logic [31:0] clk200_div;
69-
clk_divider #(
70-
.WIDTH( 32 )
71-
) cd1 (
72-
.clk( clk200 ),
73-
.nrst( nrst_once ),
74-
.ena( 1'b1 ),
75-
.out( clk200_div[31:0] )
76-
);
103+
repeat( 2 ) @(posedge clk200); // synchronous fall, controls rst_once pulse width
104+
rst_once = 1'b0;
105+
end
106+
//logic nrst_once; // declared before
107+
assign nrst_once = ~rst_once;
77108

78-
logic [31:0] clk200_div_rise;
79-
edge_detect ed1[31:0] (
80-
.clk( {32{clk200}} ),
81-
.anrst( {32{nrst_once}} ),
82-
.in( clk200_div[31:0] ),
83-
.rising( clk200_div_rise[31:0] ),
84-
.falling( ),
85-
.both( )
86-
);
87109

110+
// random pattern generation
88111
logic [31:0] rnd_data;
89112
always_ff @(posedge clk200) begin
90-
if( ~nrst_once ) begin
91-
rnd_data[31:0] <= $random( 1 ); // seeding
92-
end else begin
93-
rnd_data[31:0] <= $random;
113+
rnd_data[31:0] <= $urandom;
94114
end
115+
116+
initial forever begin
117+
@(posedge nrst);
118+
$display("[T=%0t] rnd_data[]=%h", $realtime, rnd_data[31:0]);
95119
end
96120

121+
122+
// helper start strobe appears unpredictable up to 20 clocks after nrst
97123
logic start;
98-
initial begin
99-
#0 start = 1'b0;
100-
#100 start = 1'b1;
101-
#20 start = 1'b0;
124+
initial forever begin
125+
start = 1'b0; // initialization
126+
127+
@(posedge nrst); // synchronous rise after EVERY nrst
128+
repeat( $urandom_range(0, 20) ) @(posedge clk200);
129+
start = 1'b1;
130+
131+
@(posedge clk200); // synchronous fall exactly 1 clock after rise
132+
start = 1'b0;
102133
end
103134

104-
//initial begin
105-
// #1000 $finish;
106-
//end
135+
136+
initial begin
137+
// #10000 $stop;
138+
// #10000 $finish;
139+
end
107140

108141
// Module under test ===========================================================
109142

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