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module main_tb ();
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+ initial begin
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+ // Print out time markers in nanoseconds
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+ // Example: $display("[T=%0t] start=%d", $realtime, start);
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+ $timeformat (- 9 , 3 , " ns" );
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+
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+ // seed value setting is intentionally manual to achieve repeatability between sim runs
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+ $urandom ( 1 ); // SEED value
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+ end
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+
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logic clk200;
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sim_clk_gen # (
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.FREQ ( 200_000_000 ), // in Hz
@@ -26,6 +35,28 @@ sim_clk_gen #(
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.clkd ( )
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);
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+ logic nrst_once;
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+
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+ logic [31 : 0 ] clk200_div;
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+ clk_divider # (
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+ .WIDTH ( 32 )
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+ ) cd1 (
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+ .clk ( clk200 ),
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+ .nrst ( nrst_once ),
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+ .ena ( 1'b1 ),
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+ .out ( clk200_div[31 : 0 ] )
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+ );
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+
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+ logic [31 : 0 ] clk200_div_rise;
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+ edge_detect ed1 [31 :0 ] (
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+ .clk ( { 32 { clk200}} ),
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+ .anrst ( { 32 { nrst_once}} ),
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+ .in ( clk200_div[31 : 0 ] ),
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+ .rising ( clk200_div_rise[31 : 0 ] ),
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+ .falling ( ),
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+ .both ( )
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+ );
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+
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// external device "asynchronous" clock
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logic clk33;
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logic clk33d;
@@ -40,70 +71,72 @@ sim_clk_gen #(
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.clkd ( clk33d )
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);
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+
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logic rst;
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initial begin
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- # 0 rst = 1'b0 ;
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- # 10 .2 rst = 1'b1 ;
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- # 5 rst = 1'b0 ;
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- // #10000;
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+ rst = 1'b0 ; // initialization
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+ repeat ( 1 ) @ (posedge clk200);
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+
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forever begin
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- # 9985 rst = ~ rst;
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- # 5 rst = ~ rst;
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+ repeat ( 1 ) @ (posedge clk200); // synchronous rise
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+ rst = 1'b1 ;
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+ // $urandom( 1 ); // uncomment to get the same random pattern EVERY nrst
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+
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+ repeat ( 2 ) @ (posedge clk200); // synchronous fall, controls rst pulse width
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+ rst = 1'b0 ;
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+
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+ repeat ( 100 ) @ (posedge clk200); // controls test body width
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end
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end
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-
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logic nrst;
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assign nrst = ~ rst;
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+
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logic rst_once;
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initial begin
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- # 0 rst_once = 1'b0 ;
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- # 10 .2 rst_once = 1'b1 ;
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- # 5 rst_once = 1'b0 ;
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- end
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+ rst_once = 1'b0 ; // initialization
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+ repeat ( 1 ) @ (posedge clk200);
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- logic nrst_once;
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- assign nrst_once = ~ rst_once ;
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+ repeat ( 1 ) @ ( posedge clk200); // synchronous rise
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+ rst_once = 1'b1 ;
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- logic [31 : 0 ] clk200_div;
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- clk_divider # (
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- .WIDTH ( 32 )
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- ) cd1 (
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- .clk ( clk200 ),
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- .nrst ( nrst_once ),
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- .ena ( 1'b1 ),
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- .out ( clk200_div[31 : 0 ] )
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- );
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+ repeat ( 2 ) @ (posedge clk200); // synchronous fall, controls rst_once pulse width
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+ rst_once = 1'b0 ;
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+ end
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+ // logic nrst_once; // declared before
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+ assign nrst_once = ~ rst_once;
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- logic [31 : 0 ] clk200_div_rise;
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- edge_detect ed1 [31 :0 ] (
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- .clk ( { 32 { clk200}} ),
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- .anrst ( { 32 { nrst_once}} ),
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- .in ( clk200_div[31 : 0 ] ),
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- .rising ( clk200_div_rise[31 : 0 ] ),
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- .falling ( ),
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- .both ( )
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- );
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+ // random pattern generation
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logic [31 : 0 ] rnd_data;
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always_ff @ (posedge clk200) begin
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- if ( ~ nrst_once ) begin
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- rnd_data[31 : 0 ] <= $random ( 1 ); // seeding
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- end else begin
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- rnd_data[31 : 0 ] <= $random ;
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+ rnd_data[31 : 0 ] <= $urandom ;
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end
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+
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+ initial forever begin
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+ @ (posedge nrst);
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+ $display (" [T=%0t ] rnd_data[]=%h " , $realtime , rnd_data[31 : 0 ]);
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end
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+
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+ // helper start strobe appears unpredictable up to 20 clocks after nrst
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logic start;
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- initial begin
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- # 0 start = 1'b0 ;
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- # 100 start = 1'b1 ;
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- # 20 start = 1'b0 ;
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+ initial forever begin
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+ start = 1'b0 ; // initialization
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+
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+ @ (posedge nrst); // synchronous rise after EVERY nrst
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+ repeat ( $urandom_range (0 , 20 ) ) @ (posedge clk200);
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+ start = 1'b1 ;
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+
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+ @ (posedge clk200); // synchronous fall exactly 1 clock after rise
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+ start = 1'b0 ;
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end
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- // initial begin
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- // #1000 $finish;
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- // end
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+
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+ initial begin
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+ // #10000 $stop;
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+ // #10000 $finish;
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+ end
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// Module under test ===========================================================
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