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Commits on Jun 22, 2020

• memory: tegra: Add EMC scaling sequence code for Tegra210

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• memory: tegra: Add EMC scaling support code for Tegra210

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Commits on May 20, 2020

• arm64: tegra: Add external memory controller node for Tegra210

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Commits on May 12, 2020

• clk: tegra: Remove the old emc_mux clock for Tegra210

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• clk: tegra: Implement Tegra210 EMC clock

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• clk: tegra: Export functions for EMC clock scaling

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• clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210

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• dt-bindings: memory: tegra: Add external memory controller binding for Tegra210

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Commits on Apr 15, 2020

• dt-bindings: memory: tegra: Add external memory controller binding for Tegra210

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Commits on Jun 5, 2019

• arm64: tegra: Add CPU cache topology for Tegra186

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Commits on May 2, 2019

• clocksource/drivers/tegra: Rework for compensation of suspend time

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Commits on Apr 12, 2019

• arm64: tegra: Add L2 cache topology to Tegra210

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• arm64: tegra: Enable CPU idle support for Shield

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• arm64: tegra: Enable CPU idle support for Smaug

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• arm64: tegra: Enable CPU idle support for Jetson TX1

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• arm64: tegra: Add CPU idle states properties for Tegra210

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• arm64: tegra: Fix timer node for Tegra210

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Commits on Feb 23, 2019

• soc/tegra: default select TEGRA_TIMER for Tegra210

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• clocksource/drivers/tegra: Add Tegra210 timer support

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• dt-bindings: timer: add Tegra210 timer

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Commits on Feb 7, 2019

• arm64: tegra: Enable DFLL clock on Smaug

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• arm64: tegra: Add CPU power rail regulator on Smaug

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• arm64: tegra: Enable DFLL clock on Jetson TX1

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• arm64: tegra: Add pinmux for PWM-based DFLL support on P2597

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• arm64: tegra: Add CPU clocks on Tegra210

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• arm64: tegra: Add DFLL clock on Tegra210

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Commits on Feb 6, 2019

• arm64: defconfig: Enable MAX8973 regulator

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• cpufreq: dt-platdev: add Tegra210 to blacklist

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• cpufreq: tegra124: extend to support Tegra210

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• cpufreq: tegra124: do not handle the CPU rail

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• clk: tegra: dfll: add CVB tables for Tegra210

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• clk: tegra: dfll: round down voltages based on alignment

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• clk: tegra: dfll: support PWM regulator control

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• clk: tegra: dfll: CVB calculation alignment with the regulator

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• dt-bindings: cpufreq: tegra124: remove cpu_lp clock from required properties

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