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Commits on Feb 10, 2020

• Merge pull request chipsalliance#2281 from chipsalliance/add-io-helper

  rmac-sifive

  authored
  176c5e1

Commits on Feb 8, 2020

• Add IOHelper

  rmac-sifive

  committed
  a0277e7

• Fix regression in support for Large ExtMem sizes (chipsalliance#2279)

  jerryz123

  authored
  4ca9e4d

Commits on Feb 5, 2020

• Merge pull request chipsalliance#2277 from chipsalliance/tlb_entry_public_class

  ingallsj

  authored
  319b6c4

• Merge pull request chipsalliance#2275 from chipsalliance/chicken-grant-corrupt

  aswaterman

  authored
  1c9303a

Commits on Feb 4, 2020

• If chicken CSR isn't implemented, the bits should default to false

  aswaterman

  committed
  b2474c6

• TLB: make Entry class available from other packages

  ingallsj

  committed
  bd738a7

• PLRU: multiple access update

  ingallsj

  committed
  9057b3c

• Merge pull request chipsalliance#2276 from chipsalliance/chisel3-width-widget

  mwachs5

  authored
  36d87ef

• Merge pull request chipsalliance#2270 from chipsalliance/improve-dcache-ecc-timing

  aswaterman

  authored
  5e3ce59

• TLWidthWidget: one more fix for the port to chisel3

  mwachs5

  committed
  c0bb78b

• Add feature-disable bit to suppress corrupt on GrantData

  aswaterman

  committed
  b99e79a

Commits on Feb 3, 2020

• Import RVVV v0.8 changes

  aswaterman

  committed
  ce36c6d

• Expose DTLB access port

  aswaterman

  committed
  dc68c21

• Actually run InlineInstances pass

  aswaterman

  committed
  be33e8d

• bump hardfloat

  aswaterman

  committed
  3a32cf2

Commits on Feb 1, 2020

• Merge pull request chipsalliance#2262 from chipsalliance/remove-unnecessary-type-parameter-on-register-router

  richardxia

  authored
  aa53d0e

Commits on Jan 31, 2020

• Merge pull request chipsalliance#2273 from chipsalliance/chisel3-modules-for-master

  mwachs5

  authored
  babc321

• More chisel3 fixes for WidthWidget

  mwachs5

  committed
  19d6bef

• Make PipelinedMultiplier chisel3-friendly

  aswaterman

  committed
  a360d76

• Make Repeater gen argument tolerant of chisel2-style data-as-type usage

  aswaterman

  committed
  2c8d2df

• Make Repeater gen argument tolerant of chisel2-style data-as-type usage

  

  aswaterman

  authored and

  mwachs5

  committed
  6873dee

• Port some selected modules to chisel3 for properly inferring resets in those modules.

  mwachs5

  committed
  f428f8b

Commits on Jan 28, 2020

• D$: cut d.ready -> perf.grant path

  aswaterman

  committed
  3659b5b

• D$: eliminate a data ECC -> dirty-bit path

  aswaterman

  committed
  dda5902

• D$: simplify acquire-before-release logic

  aswaterman

  committed
  e8f7734

• bumping chisel (chipsalliance#2268)

  

  debs-sifive

  authored and

  azidar

  committed
  9362ab7

Commits on Jan 25, 2020

• Bump chisel 3.2.x (chipsalliance#2261)

  

  azidar

  and

  debs-sifive

  authored
  13eed1a

Commits on Jan 22, 2020

• Diplomatic Clock Primitives (chipsalliance#1795)

  hcook

  authored
  27120ee

Commits on Jan 21, 2020

• Merge pull request chipsalliance#2265 from chipsalliance/dmactive-in-sbtotl

  ernie-sifive

  authored
  c2668be

• Don't reset sbState if dmactive is set to 0

  ernie-sifive

  committed
  bbafc9a

• Remove unused type parameter on RegisterRouter.

  richardxia

  committed
  9415d55

Commits on Jan 15, 2020

• Merge pull request chipsalliance#2257 from chipsalliance/richardxia-patch-1

  richardxia

  authored
  9ddb76e

Commits on Jan 14, 2020

• Correct spelling of TileLink in Object Model protocol description

  richardxia

  authored
  a7050af

Commits on Jan 13, 2020

• Merge pull request chipsalliance#2252 from chipsalliance/requireFifo

  ingallsj

  authored
  877c033

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