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Fix warnings and clean up a RTC driver #440

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Merged
merged 1 commit into from
Mar 14, 2023
Merged

Fix warnings and clean up a RTC driver #440

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66 changes: 2 additions & 64 deletions esp-hal-common/src/rtc_cntl/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -84,23 +84,18 @@ impl Clock for RtcSlowClock {
RtcSlowClock::RtcSlowClockRtc => HertzU32::Hz(150_000),
#[cfg(esp32s2)]
RtcSlowClock::RtcSlowClockRtc => HertzU32::Hz(90_000),
#[cfg(any(esp32c2, esp32c3, esp32c6, esp32s3))]
#[cfg(any(esp32c2, esp32c3, esp32s3))]
RtcSlowClock::RtcSlowClockRtc => HertzU32::Hz(136_000),
RtcSlowClock::RtcSlowClock32kXtal => HertzU32::Hz(32_768),
#[cfg(any(esp32, esp32s2))]
RtcSlowClock::RtcSlowClock8mD256 => HertzU32::Hz(8_500_000 / 256),
#[cfg(any(esp32c2, esp32c3, esp32s3))]
RtcSlowClock::RtcSlowClock8mD256 => HertzU32::Hz(17_500_000 / 256),
#[cfg(esp32c6)]
RtcSlowClock::RtcSlowClock32kRc => HertzU32::Hz(32_768),
#[cfg(esp32c6)]
RtcSlowClock::RtcCalInternalOsc => HertzU32::Hz(32_768),
#[cfg(esp32c6)]
RtcSlowClock::RtcCalRcFast => HertzU32::Hz(150_000),
}
}
}

#[allow(unused)]
#[cfg(not(esp32c6))]
#[derive(Debug, Clone, Copy)]
/// Clock source to be calibrated using rtc_clk_cal function
Expand Down Expand Up @@ -190,28 +185,10 @@ impl RtcClock {
}
}

#[cfg(esp32c6)]
fn enable_8m(clk_8m_en: bool, _d256_en: bool) {
let pmu = unsafe { &*PMU::PTR };

if clk_8m_en {
pmu.hp_sleep_lp_ck_power
.modify(|_, w| w.hp_sleep_xpd_fosc_clk().set_bit());

unsafe { ets_delay_us(50) };
} else {
pmu.hp_sleep_lp_ck_power
.modify(|_, w| w.hp_sleep_xpd_fosc_clk().clear_bit());
}
}

/// Get main XTAL frequency
/// This is the value stored in RTC register RTC_XTAL_FREQ_REG by the
/// bootloader, as passed to rtc_clk_init function.
fn get_xtal_freq() -> XtalClock {
#[cfg(esp32c6)]
let xtal_freq_reg = unsafe { &*LP_AON::PTR }.store4.read().bits();
#[cfg(not(esp32c6))]
let xtal_freq_reg = unsafe { &*RTC_CNTL::PTR }.store4.read().bits();

// Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are stored as two copies in
Expand Down Expand Up @@ -251,21 +228,6 @@ impl RtcClock {
}
}

/// Get the RTC_SLOW_CLK source
#[cfg(esp32c6)]
fn get_slow_freq() -> RtcSlowClock {
let lp_clrst = unsafe { &*LP_CLKRST::ptr() };

let slow_freq = lp_clrst.lp_clk_conf.read().slow_clk_sel().bits();
match slow_freq {
0 => RtcSlowClock::RtcSlowClockRtc,
1 => RtcSlowClock::RtcSlowClock32kXtal,
2 => RtcSlowClock::RtcSlowClock32kRc,
3 => RtcSlowClock::RtcCalInternalOsc,
_ => unreachable!(),
}
}

/// Select source for RTC_SLOW_CLK
#[cfg(not(esp32c6))]
fn set_slow_freq(slow_freq: RtcSlowClock) {
Expand Down Expand Up @@ -295,11 +257,6 @@ impl RtcClock {
};
}

#[cfg(esp32c6)]
fn set_slow_freq(slow_freq: RtcSlowClock) {
todo!()
}

/// Select source for RTC_FAST_CLK
#[cfg(not(esp32c6))]
fn set_fast_freq(fast_freq: RtcFastClock) {
Expand All @@ -316,11 +273,6 @@ impl RtcClock {
};
}

#[cfg(esp32c6)]
fn set_fast_freq(fast_freq: RtcFastClock) {
todo!()
}

/// Calibration of RTC_SLOW_CLK is performed using a special feature of
/// TIMG0. This feature counts the number of XTAL clock cycles within a
/// given number of RTC_SLOW_CLK cycles.
Expand Down Expand Up @@ -469,14 +421,6 @@ impl RtcClock {
cal_val
}

/// Calibration of RTC_SLOW_CLK is performed using a special feature of
/// TIMG0. This feature counts the number of XTAL clock cycles within a
/// given number of RTC_SLOW_CLK cycles.
#[cfg(esp32c6)]
fn calibrate_internal(cal_clk: RtcCalSel, slowclk_cycles: u32) -> u32 {
todo!()
}

/// Measure ratio between XTAL frequency and RTC slow clock frequency
fn get_calibration_ratio(cal_clk: RtcCalSel, slowclk_cycles: u32) -> u32 {
let xtal_cycles = RtcClock::calibrate_internal(cal_clk, slowclk_cycles) as u64;
Expand Down Expand Up @@ -509,12 +453,6 @@ impl RtcClock {
RtcSlowClock::RtcSlowClock32kXtal => RtcCalSel::RtcCal32kXtal,
#[cfg(not(esp32c6))]
RtcSlowClock::RtcSlowClock8mD256 => RtcCalSel::RtcCal8mD256,
#[cfg(esp32c6)]
RtcSlowClock::RtcSlowClock32kRc => RtcCalSel::RtcCal32kRc,
#[cfg(esp32c6)]
RtcSlowClock::RtcCalInternalOsc => RtcCalSel::RtcCalInternalOsc,
#[cfg(esp32c6)]
RtcSlowClock::RtcCalRcFast => RtcCalSel::RtcCalRcFast,
},
1024,
);
Expand Down
25 changes: 0 additions & 25 deletions esp-hal-common/src/rtc_cntl/rtc/esp32c6.rs
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -275,21 +275,6 @@ pub struct RtcClock;
impl RtcClock {
const CAL_FRACT: u32 = 19;

/// Enable or disable 8 MHz internal oscillator
fn enable_8m(clk_8m_en: bool, _d256_en: bool) {
let pmu = unsafe { &*PMU::PTR };

if clk_8m_en {
pmu.hp_sleep_lp_ck_power
.modify(|_, w| w.hp_sleep_xpd_fosc_clk().set_bit());

unsafe { ets_delay_us(50) };
} else {
pmu.hp_sleep_lp_ck_power
.modify(|_, w| w.hp_sleep_xpd_fosc_clk().clear_bit());
}
}

/// Get main XTAL frequency
/// This is the value stored in RTC register RTC_XTAL_FREQ_REG by the
/// bootloader, as passed to rtc_clk_init function.
Expand Down Expand Up @@ -625,16 +610,6 @@ impl RtcClock {
cal_val
}

/// Measure ratio between XTAL frequency and RTC slow clock frequency
fn get_calibration_value(cal_clk: RtcCalSel, slowclk_cycles: u32) -> u32 {
let xtal_freq = RtcClock::get_xtal_freq();
let xtal_cycles = RtcClock::calibrate_internal(cal_clk, slowclk_cycles) as u64;
let divider = xtal_freq.mhz() as u64 * slowclk_cycles as u64;
let period_64 = ((xtal_cycles << RtcClock::CAL_FRACT) + divider / 2u64 - 1u64) / divider;

(period_64 & u32::MAX as u64) as u32
}

/// Measure RTC slow clock's period, based on main XTAL frequency
///
/// This function will time out and return 0 if the time for the given
Expand Down