soc/uart: add shared UARTBone mux - #2506
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Add a shared serial PHY mux for SoCs that enable UARTBone together with the regular UART. When UARTBone and the serial/crossover UART are both selected, SoCCore now uses the mux automatically and the selector resets to UARTBone mode. The UART uartbone CSR selects whether the serial pins are connected to UARTBone or directly to the CPU UART. add_uartbone() can use the mux virtual PHY, and the BIOS uartbone command switches the shared serial pins back to UARTBone from the regular console. This addresses the UARTBone/normal UART sharing use-case from #1959 and is based on the original mux idea proposed by Joshua Wise (@jwise). Add tests for mux routing, validation, automatic SoC integration, and the regular UART escape path.
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This adds a shared serial PHY mux for SoCs that enable UARTBone together with the regular UART.
When UARTBone and the serial/crossover UART are both selected, SoCCore now uses the mux automatically and the selector resets to UARTBone mode. The UART
uartboneCSR selects whether the shared serial pins are connected to UARTBone or directly to the CPU UART, and the BIOSuartbonecommand switches the pins back to UARTBone from the regular UART console.This addresses the UARTBone/normal UART sharing use-case from #1959 and is based on the original mux idea proposed by Joshua Wise (@jwise).
Tests:
python3 -m py_compile litex/soc/cores/uart.py litex/soc/integration/soc.py test/cores/test_uart.py test/soc/test_soc.pypytest -q test/cores/test_uart.py test/soc/test_soc.py test/software/test_bios_console.pygcccompile-check forcmd_bios.cwith UARTBone CSR stubs