Add dynamic mux for UARTBone / normal UART - #1959
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…ll-bandwidth UART, but enable debuggability as needed
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Thanks again for the original proposal and detailed explanation. I opened a refreshed implementation in #2506 based on the same UARTBone/normal UART mux idea. Compared with this PR, the new version keeps the user-facing path simpler:
The commit message also credits the original idea here. If this direction looks good, we can continue from #2506 as the current integration point. |
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One problem with debugging a single-UART system is that the system will always block if a UARTBone client is not connected. This is particularly annoying if, for instance, your vendor's RAM update tools do not work right (I'm looking at you, Efinix...), and you need the UARTBone to iterate on firmware -- but, once you have a build, you would like to have a UART that does not block. (In my system, I have two FPGAs talking to each other, and I am probably developing one or the other at a time, and I would like to be able to distribute a bitstream to the customer that just happily boots without any drama, for instance.)
This PR solves this by modifying the
UARTCrossoverto have adebug_enCSR, and apad_phyinput. Whendebug_enis turned on (the default, on reset), then the system behaves exactly like it previously did. However, switching offdebug_enmeans that the crossover internal UART and UARTbone are disconnected, and theUARTCrossover'ssourceandsinkare actually connected to the pads of the outer world -- basically, passing the UART straight through.To use this, I do something like this:
There is a little bit of WIP here: the simplest way to wire this up was through the old
crossover+uartbonepath that is now deprecated. I undeprecate this by commenting out the deprecation! But obviously I would like feedback on what you think the better way is to do this.