(0.21.0) AArch64: Create new instruction classes to handle alias instructions #61
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added 2 commits
June 9, 2020 14:21
This commit introduces 3 new instruction classes: - ARM64Trg1ZeroSrc1Instruction - ARM64ZeroSrc1ImmInstruction - ARM64ZeroSrc2Instruction These classes are used to handle alias instructions using the `xzr` register. For example, `cmp` instruction is an alias of `subs` instruction with `xzr` as target register. The current implementation of helper functions for generating alias instructions such as `generateCompareImmInstruction` allocates a virtual register and associates it with `xzr` using register dependency. Ths problem with this approach is: - That register dependency interferes other register dependencies. - Those helper functions cannot be used to generate instructions after register assignment phase. (generating prologue/epilogue) The new implementation of those helper functions use newly introduced instruction classes instead of allocating virtual register for `xzr`. Those instruction classes does not hold a register for `xzr`. `generateBinaryEncoding` of those classes encodes register number of `xzr` to the appropriate position of instructions. Signed-off-by: Akira Saitoh <saiaki@jp.ibm.com>
Signed-off-by: Akira Saitoh <saiaki@jp.ibm.com>
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This is an AArch64-specific change. It was committed to OMR prior to the OpenJ9 split for 0.21.0, but because the OMR Acceptance build was broken it did not promote and wasn't part of the split. |
0xdaryl
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Jun 9, 2020
knn-k
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Jun 9, 2020
This commit implements ARM64Trg1Src2ZeroInstruction class so that we can stop setting register dependencies on the zero register in generating instructions for integer multiply. This commit also contains the following changes: - Implement and use insertZeroRegister() functions in classes introduced by eclipse-openj9#61 - Remove the code for printing "cmp" from ARM64Trg1Src2Instruction (It was moved to ARM64ZeroSrc2Instruction) Original PRs for master: eclipse-omr/omr#5289, eclipse-omr/omr#5290 Signed-off-by: KONNO Kazuhiro <konno@jp.ibm.com>
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This commit introduces 3 new instruction classes:
These classes are used to handle alias instructions using the xzr register.
For example, cmp instruction is an alias of subs instruction with xzr
as target register.
The current implementation of helper functions for generating alias instructions
such as generateCompareImmInstruction allocates a virtual register
and associates it with xzr using register dependency.
Ths problem with this approach is:
register assignment phase. (generating prologue/epilogue)
The new implementation of those helper functions use newly introduced
instruction classes instead of allocating virtual register for xzr.
Those instruction classes does not hold a register for xzr.
generateBinaryEncoding of those classes encodes register number of xzr
to the appropriate position of instructions.
Master PRs:
eclipse-omr/omr#5280
eclipse-omr/omr#5288
Signed-off-by: Akira Saitoh saiaki@jp.ibm.com