Implement binary encoding for POWER10 PC-relative loads and stores #5371
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aviansie-ben
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0xdaryl,
charliegracie and
mstoodle
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gita-omr
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gita-omr
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gita-omr
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zl-wang
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Jul 15, 2020
In POWER10, a number of new prefixed load and store instructions have been added. These allow for 34-bit offsets, but crucially they also have a bit that causes the load/store to occur relative to the address of the current instruction. This can be used in a number of interesting ways and will allow us to completely remove the pTOC on POWER10 systems, since we can replace pTOC loads with PC-relative loads. Support for using these PC-relative loads and stores to load at an offset from a TR::LabelSymbol has now been added to the Power codegen. Signed-off-by: Ben Thomas <ben@benthomas.ca>
Previously, PC-relative loads and stores could only be encoded by giving their offset relative to a label. Now, support has been added to specify the offset directly. While this may seem less than useful since it's not normally possible to know exact offsets to surrounding instructions due to e.g. boundary avoidance for prefixed instructions, there is one particular use case: when the displacement is meant to be patched, it is necessary to force a displacement of 0 to be used, which cannot be done using labels. Signed-off-by: Ben Thomas <ben@benthomas.ca>
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fjeremic
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This PR adds binary encoder support for encoding PC-relative offsets on the new POWER10 prefixed loads and stores. There are currently two different ways of specifying the displacement:
TR::LabelSymbolThe first method is meant to be the standard way of doing this, with the second method existing only to allow the displacement field to be forced to be 0 when a PC-relative load/store's displacement will be patched.