Fix error with incorrect encoder internal flow control. It did not wo…

…rk at peak load
dshekhalev · Feb 2, 2023 · c68da7a · c68da7a
1 parent 6421279
commit c68da7a
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Showing 2 changed files with 12 additions and 3 deletions.
diff --git a/rtl/ldpc_dvb/enc/ldpc_dvb_enc_ctrl.sv b/rtl/ldpc_dvb/enc/ldpc_dvb_enc_ctrl.sv
@@ -25,6 +25,7 @@
   logic       ldpc_dvb_enc_ctrl__ocycle_read    ;
   cycle_idx_t ldpc_dvb_enc_ctrl__ocycle_idx     ;
   //
+  logic       ldpc_dvb_enc_ctrl__ip_read_busy   ;
   logic       ldpc_dvb_enc_ctrl__op_read        ;
   strb_t      ldpc_dvb_enc_ctrl__op_strb        ;
   row_t       ldpc_dvb_enc_ctrl__op_row_idx     ;
@@ -54,6 +55,7 @@
     .ocycle_read    ( ldpc_dvb_enc_ctrl__ocycle_read    ) ,
     .ocycle_idx     ( ldpc_dvb_enc_ctrl__ocycle_idx     ) ,
     //
+    .ip_read_busy   ( ldpc_dvb_enc_ctrl__ip_read_busy   ) ,
     .op_read        ( ldpc_dvb_enc_ctrl__op_read        ) ,
     .op_strb        ( ldpc_dvb_enc_ctrl__op_strb        ) ,
     .op_row_idx     ( ldpc_dvb_enc_ctrl__op_row_idx     )
@@ -70,6 +72,7 @@
   assign ldpc_dvb_enc_ctrl__iused_row      = '0 ;
   assign ldpc_dvb_enc_ctrl__icycle_max_num = '0 ;
   assign ldpc_dvb_enc_ctrl__ip_busy        = '0 ;
+  assign ldpc_dvb_enc_ctrl__ip_read_busy   = '0 ;
 
 
 
@@ -104,6 +107,7 @@ module ldpc_dvb_enc_ctrl
   ocycle_read    ,
   ocycle_idx     ,
   //
+  ip_read_busy   ,
   op_read        ,
   op_strb        ,
   op_row_idx
@@ -131,11 +135,12 @@ module ldpc_dvb_enc_ctrl
   input  cycle_idx_t icycle_max_num ;
   //
   output logic       ostart         ;
-  //
+  // parity logic interface
   input  logic       ip_busy        ;
   output logic       ocycle_read    ;
   output cycle_idx_t ocycle_idx     ;
-  //
+  // parity ram read interface
+  input  logic       ip_read_busy   ;
   output logic       op_read        ;
   output strb_t      op_strb        ;
   output row_t       op_row_idx     ;
@@ -194,7 +199,7 @@ module ldpc_dvb_enc_ctrl
         cWAIT_DATA_STATE    : state <= !ip_busy                  ? cDO_P_STATE      : cWAIT_DATA_STATE;
         // do IRA coding
         cDO_P_STATE         : state <= row_cnt.done              ? cWAIT_DO_P_STATE : cDO_P_STATE;
-        cWAIT_DO_P_STATE    : state <= cDONE_STATE;
+        cWAIT_DO_P_STATE    : state <= !ip_read_busy             ? cDONE_STATE      : cWAIT_DO_P_STATE;
         //
         cDONE_STATE         : state <= cWAIT_STATE;
       endcase

diff --git a/rtl/ldpc_dvb/enc/ldpc_dvb_enc_engine.sv b/rtl/ldpc_dvb/enc/ldpc_dvb_enc_engine.sv
@@ -219,6 +219,7 @@ module ldpc_dvb_enc_engine
   logic                       ctrl__ocycle_read    ;
   cycle_idx_t                 ctrl__ocycle_idx     ;
   //
+  logic                       ctrl__ip_read_busy   ;
   logic                       ctrl__op_read        ;
   strb_t                      ctrl__op_strb        ;
   row_t                       ctrl__op_row_idx     ;
@@ -403,6 +404,7 @@ module ldpc_dvb_enc_engine
     .ocycle_read    ( ctrl__ocycle_read    ) ,
     .ocycle_idx     ( ctrl__ocycle_idx     ) ,
     //
+    .ip_read_busy   ( ctrl__ip_read_busy   ) ,
     .op_read        ( ctrl__op_read        ) ,
     .op_strb        ( ctrl__op_strb        ) ,
     .op_row_idx     ( ctrl__op_row_idx     )
@@ -421,6 +423,8 @@ module ldpc_dvb_enc_engine
 
   assign ctrl__ip_busy        = rdat_val[cBS_DELAY-3]  ; // 2 tick is pram read latency (can use for codes used_row >= 4)
 
+  assign ctrl__ip_read_busy   = mux__owrite; // wait until write all to buffer
+
   //------------------------------------------------------------------------------------------------------
   // barrel shifter
   //------------------------------------------------------------------------------------------------------