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Remade decoder iterations flow control. Add 2 types of possible FIFO …
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…SRL/RAMB type, optimize register using and RAMB using for small codeword.
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@dshekhalev
dshekhalev committed Feb 1, 2023
1 parent c527584 commit 6421279
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2 changes: 1 addition & 1 deletion README.md
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Expand Up @@ -13,7 +13,7 @@ The library contain:
7. 3GPP LDPC code
8. 3GPP Polar code
9. Soft decision Golay code
10. DVB-S LDPC code
10. DVB-S2 LDPC code
11. CCSDS Turbo code
12. 4D-8PSK TCM code
13. Hamming code
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6 changes: 3 additions & 3 deletions rtl/ldpc_dvb/README.md
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Expand Up @@ -20,14 +20,14 @@ Decoder settings : coderate = 1/2, block length = 64800 bits, 8 LLR/bits per tic

pNODE_W = 6 bits (optimal codegain for 4 bit LLR)

Decoder : LUT/REG/RAMB 56k/69k/133.5 iface >250MHz, core >250MHz (480Mbps -> 240Mbps)
Decoder : LUT/REG/RAMB 59k/63k/97.5 iface >250MHz, core >250MHz (480Mbps -> 240Mbps)

pNODE_W = 5 bits (good codegain for 4 bit LLR)

Decoder : LUT/REG/RAMB 47k/61k/118.5 iface >250MHz, core >250MHz (480Mbps -> 240Mbps)
Decoder : LUT/REG/RAMB 49k/55k/87.5 iface >250MHz, core >250MHz (480Mbps -> 240Mbps)

pNODE_W = 4 bits (worst codegain for 4 bit LLR)

Decoder : LUT/REG/RAMB 38k/53k/103.5 iface >250MHz, core >250MHz (480Mbps -> 240Mbps)
Decoder : LUT/REG/RAMB 40k/48k/77.5 iface >250MHz, core >250MHz (480Mbps -> 240Mbps)

Attention: The coder and decoder correspond each other but can have different bit order with standard codes. Strongly speaking it's not DVB-S2 codec, because there is no parity bits reorder inside. It should be done external of codec during bit interleaving procedure !!!
81 changes: 50 additions & 31 deletions rtl/ldpc_dvb/dec/ldpc_dvb_dec_2d_engine.sv
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Expand Up @@ -2,21 +2,25 @@
parameter int pLLR_W = 8 ;
parameter int pNODE_W = 8 ;
parameter int pLLR_W = 8 ;
parameter int pNODE_W = 8 ;
//
parameter int pRADDR_W = 8 ;
parameter int pWADDR_W = 8 ;
parameter int pRADDR_W = 8 ;
parameter int pWADDR_W = 8 ;
//
parameter int pTAG_W = 4 ;
//
parameter int pTAG_W = 4 ;
parameter int pERR_W = 16 ;
//
parameter int pERR_W = 16 ;
parameter bit pCODEGR = 1 ;
//
parameter int pCNORM_FACTOR = 6 ;
parameter int pCNORM_FACTOR = 6 ;
//
parameter bit pUSE_SC_MODE = 1 ;
parameter bit pDO_LLR_INVERSION = 1 ;
parameter bit pUSE_SRL_FIFO = 1 ;
parameter bit pUSE_SC_MODE = 1 ;
//
parameter bit pFIX_MODE = 1 ;
parameter bit pFIX_MODE = 1 ;
Expand Down Expand Up @@ -63,9 +67,11 @@
//
.pERR_W ( pERR_W ) ,
//
.pCODEGR ( pCODEGR ) ,
.pCNORM_FACTOR ( pCNORM_FACTOR ) ,
//
.pDO_LLR_INVERSION ( pDO_LLR_INVERSION ) ,
.pUSE_SRL_FIFO ( pUSE_SRL_FIFO ) ,
.pUSE_SC_MODE ( pUSE_SC_MODE ) ,
//
.pFIX_MODE ( pFIX_MODE )
Expand Down Expand Up @@ -166,15 +172,19 @@ module ldpc_dvb_dec_2d_engine
//
parameter int pERR_W = 16 ;
//
parameter int pCNORM_FACTOR = 6 ;
parameter int pCNORM_FACTOR = 7 ; // horizontal step normalization factor

parameter bit pDO_LLR_INVERSION = 1 ; // do metric inversion inside decoder

parameter bit pDO_LLR_INVERSION = 0 ;
parameter bit pUSE_SRL_FIFO = 1 ; // use SRL based internal FIFO
//
parameter int pFIX_MODE = 0 ;
parameter int pFIX_MODE = 0 ; // fix mode decoder

`include "../ldpc_dvb_constants.svh"
`include "ldpc_dvb_dec_types.svh"

parameter bit pCODEGR = cCODEGR_LARGE ; // maximum used graph short(0)/large(1)

//------------------------------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------------------------------
Expand Down Expand Up @@ -212,10 +222,10 @@ module ldpc_dvb_dec_2d_engine
//
//------------------------------------------------------------------------------------------------------

localparam int cNODE_RAM_ADDR_W = cHS_CYCLE_W ;
localparam int cNODE_RAM_ADDR_W = pCODEGR ? cHS_CYCLE_W : cHS_SHORT_CYCLE_W;
localparam int cNODE_RAM_DAT_W = pNODE_W * cZC_MAX;

localparam int cSTATE_RAM_ADDR_W = cHS_CYCLE_W ;
localparam int cSTATE_RAM_ADDR_W = cNODE_RAM_ADDR_W ;
localparam int cSTATE_RAM_DAT_W = (1 + (pUSE_SC_MODE ? $bits(node_state_t) : 0)) * cZC_MAX; // +1 for syndrome decision

//------------------------------------------------------------------------------------------------------
Expand Down Expand Up @@ -337,6 +347,8 @@ module ldpc_dvb_dec_2d_engine
zdat_t vnode__obitdat ;
zdat_t vnode__obiterr ;
col_t vnode__obitaddr ;
//
logic vnode__obusy ;

//------------------------------------------------------------------------------------------------------
// Hs "generator"
Expand Down Expand Up @@ -519,9 +531,9 @@ module ldpc_dvb_dec_2d_engine
assign ctrl__iused_row = hs_gen__oused_row;
assign ctrl__icycle_max_num = hs_gen__ocycle_max_num;

assign ctrl__ivnode_busy = (ctrl__ocycle_read | vnode__ovnode_val);
assign ctrl__ivnode_busy = (ctrl__ocycle_read | vnode__obusy);

assign ctrl__icnode_busy = (ctrl__ocycle_read | cnode__ocnode_val);
assign ctrl__icnode_busy = (ctrl__ocycle_read | cnode__obusy);
assign ctrl__icnode_decfail = cnode__odecfail;

//------------------------------------------------------------------------------------------------------
Expand Down Expand Up @@ -551,7 +563,7 @@ module ldpc_dvb_dec_2d_engine
.ordat ( node_ram__ordat )
);

assign node_ram__iraddr = hs_gen__ocycle_node_raddr;
assign node_ram__iraddr = hs_gen__ocycle_node_raddr[cNODE_RAM_ADDR_W-1 : 0];

always_comb begin
for (int z = 0; z < cZC_MAX; z++) begin
Expand All @@ -563,15 +575,15 @@ module ldpc_dvb_dec_2d_engine

always_ff @(posedge iclk) begin
if (iclkena) begin
if (ctrl__oc_nv_mode) begin
node_ram__iwrite <= cnode__ocnode_val ;
node_ram__iwaddr <= cnode__ocnode_addr ;
node_ram_wdat <= cnode__ocnode ;
node_ram__iwrite <= cnode__ocnode_val | vnode__ovnode_val;
//
if (cnode__ocnode_val) begin
node_ram__iwaddr <= cnode__ocnode_addr[cNODE_RAM_ADDR_W-1 : 0];
node_ram_wdat <= cnode__ocnode;
end
else begin
node_ram__iwrite <= vnode__ovnode_val ;
node_ram__iwaddr <= vnode__ovnode_addr ;
node_ram_wdat <= vnode__ovnode ;
node_ram__iwaddr <= vnode__ovnode_addr[cNODE_RAM_ADDR_W-1 : 0];
node_ram_wdat <= vnode__ovnode;
end
end
end
Expand Down Expand Up @@ -603,12 +615,12 @@ module ldpc_dvb_dec_2d_engine
.ordat ( state_ram__ordat )
);

assign state_ram__iraddr = hs_gen__ocycle_node_raddr;
assign state_ram__iraddr = hs_gen__ocycle_node_raddr[cSTATE_RAM_ADDR_W-1 : 0];

always_ff @(posedge iclk) begin
if (iclkena) begin
state_ram__iwrite <= vnode__ovnode_val;
state_ram__iwaddr <= vnode__ovnode_addr;
state_ram__iwaddr <= vnode__ovnode_addr[cSTATE_RAM_ADDR_W-1 : 0];
if (pUSE_SC_MODE) begin
state_ram__iwdat[cSTATE_RAM_DAT_W-1 -: cZC_MAX] <= vnode__ovnode_hd;
//
Expand Down Expand Up @@ -642,9 +654,12 @@ module ldpc_dvb_dec_2d_engine

ldpc_dvb_dec_cnode
#(
.pLLR_W ( pLLR_W ) ,
.pNODE_W ( pNODE_W ) ,
.pNORM_FACTOR ( pCNORM_FACTOR )
.pLLR_W ( pLLR_W ) ,
.pNODE_W ( pNODE_W ) ,
//
.pNORM_FACTOR ( pCNORM_FACTOR ) ,
//
.pUSE_SRL_FIFO ( pUSE_SRL_FIFO )
)
cnode
(
Expand Down Expand Up @@ -691,7 +706,9 @@ module ldpc_dvb_dec_2d_engine
.pNODE_W ( pNODE_W ) ,
//
.pUSE_SC_MODE ( pUSE_SC_MODE ) ,
.pDO_LLR_INVERSION ( pDO_LLR_INVERSION )
.pDO_LLR_INVERSION ( pDO_LLR_INVERSION ) ,
//
.pUSE_SRL_FIFO ( pUSE_SRL_FIFO )
)
vnode
(
Expand Down Expand Up @@ -720,7 +737,9 @@ module ldpc_dvb_dec_2d_engine
.obiteop ( vnode__obiteop ) ,
.obitdat ( vnode__obitdat ) ,
.obiterr ( vnode__obiterr ) ,
.obitaddr ( vnode__obitaddr )
.obitaddr ( vnode__obitaddr ) ,
//
.obusy ( vnode__obusy )
);

assign vnode__istart = ctrl__ocycle_start;// & !ctrl__oc_nv_mode;
Expand Down
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