New: Support FST (#32)

.gitignore

@@ -105,11 +105,13 @@
 example/svut_h.sv
 example/*.out
 example/*.vcd
+example/*.fst
 example/build/
 example/log
 test/svut_h.sv
 test/*.out
 test/*.vcd
+test/*.fst
 test/build/
 test/log
 debug

example/ffd_testbench.sv

@@ -43,14 +43,13 @@ module ffd_testbench();
     .q     (q)
     );
 
-
     // An example to create a clock for icarus:
     initial aclk = 0;
     always #2 aclk <= ~aclk;
 
     // An example to dump data for visualization
     initial begin
-        $dumpfile("waveform.vcd");
+        $dumpfile("ffd_testbench.vcd");
         $dumpvars(0, ffd_testbench);
     end
 

svut/svutRun.py

@@ -196,6 +196,8 @@ def create_iverilog(args, test):
 
     cmds = []
 
+    testname = os.path.basename(test).split(".")[0]
+
     if not os.path.isfile("svut.out"):
         print_event("Testbench executable not found. Will build it")
         args.run_only = False
@@ -234,6 +236,10 @@ def create_iverilog(args, test):
             cmd += args.vpi + " "
 
         cmd += "svut.out "
+
+        if args.fst:
+            cmd += "-fst "
+
         cmds.append(cmd)
 
     return cmds
@@ -256,13 +262,18 @@ def create_verilator(args, test):
     # Build testbench executable
     if not args.run_only:
 
-        cmd = """verilator -Wall --trace --Mdir build +1800-2012ext+sv """
+        cmd = """verilator -Wall --Mdir build +1800-2012ext+sv """
         cmd += """+1800-2005ext+v -Wno-STMTDLY -Wno-UNUSED -Wno-UNDRIVEN -Wno-PINCONNECTEMPTY """
         cmd += """-Wpedantic -Wno-VARHIDDEN -Wno-lint """
 
         if args.define:
             cmd += get_defines(args.define)
 
+        if args.fst:
+            cmd += "--trace-fst "
+        else:
+            cmd += "--trace "
+
         if args.dotfile:
 
             dotfiles = ""
@@ -374,6 +385,9 @@ def main():
                         help='''A string of arguments passed as is to Icarus (only), separated \
                                 by a space ex: -vpi "-M. -mMyVPI"''')
 
+    parser.add_argument('-fst', dest='fst', default=False, action='store_true',
+                        help="Choose FST format for waveform. If not used, select VCD")
+
     # SVUT Execution options
 
     parser.add_argument('-run-only', dest='run_only', default=False, action='store_true',

svut/template.cpp

@@ -1,21 +1,47 @@
 #include "build/V${name}_testbench.h"
 #include "verilated.h"
+// To uncomment if use FST format
+// #include "verilated_fst_c.h"
+
 
 int main(int argc, char** argv, char** env) {
 
+    // To uncomment if use FST format
+    // Initialize trace object for FST
+    // VerilatedFstC* tfp = new VerilatedFstC;
+
+    // Construct a VerilatedContext to hold simulation time, etc.
+    // Multiple modules (made later below with Vtop) may share the same
+    // context to share time, or modules may have different contexts if
+    // they should be independent from each other.
+    // Using unique_ptr is similar to
+    // "VerilatedContext* contextp = new VerilatedContext" then deleting at end.
+    const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
+    // Set debug level, 0 is off, 9 is highest presently used
+    // May be overridden by commandArgs argument parsing
+    contextp->debug(0);
+    // Verilator must compute traced signals
+    contextp->traceEverOn(true);
+    // Pass arguments so Verilated code can see them, e.g. $value$plusargs
+    // This needs to be called before you create any model
     Verilated::commandArgs(argc, argv);
     V${name}_testbench* top = new V${name}_testbench;
-    int timer = 0;
+
+    // To uncomment if use FST format
+    // Attach FST trace to the model
+    // top->trace(tfp, 99);  // Depth of 99 levels
+    // tfp->open("waveform.fst");  // Open FST file
 
     // Simulate until $$finish()
     while (!Verilated::gotFinish()) {
-
         // Evaluate model;
         top->eval();
     }
 
     // Final model cleanup
     top->final();
+    // To uncomment if use FST format
+    // tfp->close();  // Close the FST file
 
     // Destroy model
     delete top;

svut/template.sv

@@ -16,7 +16,11 @@ ${module_inst}
 
     // To dump data for visualization:
     // initial begin
+    //     Default wavefile name with VCD format
     //     $$dumpfile("${name}_testbench.vcd");
+    //     Or use FST format with -fst argument
+    //     $$dumpfile("${name}_testbench.fst");
+    //     Dump all the signals of the design
     //     $$dumpvars(0, ${name}_testbench);
     // end