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ARM64-SVE: Implement IF_SVE_DL_2A, IF_SVE_DZ_1A, IF_SVE_EA_1A #97068
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch Issue DetailsNext batch of encodings from #94549. JitDisasm output:
cstool output:
Note that
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch Issue DetailsNext batch of encodings from #94549. JitDisasm output:
cstool output:
Note that
|
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Otherwise, LGTM
src/coreclr/jit/emitarm64.cpp
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assert(isValidGeneralDatasize(id->idOpSize())); // X | ||
case IF_SVE_DL_2A: // ........xx...... .....l.NNNNddddd -- SVE predicate count (predicate-as-counter) | ||
assert(id->idOpSize() == EA_8BYTE); | ||
// assert(isValidVectorLength()); // l |
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Commented assert?
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Thanks for catching that; removed.
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LGTM. Thanks!
Next batch of encodings from #94549.
JitDisasm output:
cstool output:
Note that
fmov
is an alias forfdup
, which is why we don't see the latter in the outputs. Aside from the differences in printing the predicate register numbers, the outputs look the same. cc @dotnet/arm64-contrib.