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[RISC-V] Implement emulate single step feature. #94711

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Merged
merged 3 commits into from
Nov 15, 2023
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viewizard
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With this changes managed debugger (tested with netcoredbg) can continue execution after break on managed breakpoint.
Note, RiscV64SingleStepper code is close to Arm64SingleStepper code except arch-related methods like TryEmulate(), GetReg(), SetReg().

CC @clamp03 @wscho77 @HJLeee @JongHeonChoi @t-mustafin @gbalykov @brucehoult

Error message  /home/clamp/runtime/src/coreclr/debug/inc/riscv64/primitives.h:52:5: error: integer value -1 is outside the valid range of values [0, 255] for this enumeration type [-Wenum-constexpr-conversion]
              (CorDebugRegister)(-1), // X0 is zero register that is not a real register. We need padding here for proper mapping with ICorDebugInfo::RegNum.
              ^
@ghost ghost added area-VM-coreclr community-contribution Indicates that the PR has been added by a community member labels Nov 14, 2023
@viewizard viewizard changed the title Riscv64 [RISC-V] Implement emulate single step feature. Nov 14, 2023
@clamp03 clamp03 added the arch-riscv Related to the RISC-V architecture label Nov 14, 2023
// 21 | 20 1 | 0
// inst[31]/sign | inst[19:12] | inst[20] | inst[30:25] | inst[24:21] | 0
uint64_t imm = SignExtend((BitExtract(opcode, 30, 21) << 1) | (BitExtract(opcode, 20, 20) << 11) |
(BitExtract(opcode, 19, 12) << 12) | (BitExtract(opcode, 31, 31) << 20), 21);
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I think sign bit (inst[31] << 20) in inst is checked in SignExtend with (1ull << 20) not 21. Could you check it is correct?

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Thanks! I miss count bits when write comments and just set wrong sign bit even didn't looked at real sign bit that I moved properly -_- , should be

            //      20       | 19                                               1 | 0
            // inst[31]/sign | inst[19:12] | inst[20] | inst[30:25] | inst[24:21] | 0

will fix here and other lines too.

// 13 | 12 1 | 0
// inst[31]/sign | inst[7] | inst[30:25] | inst[11:8] | 0
uint64_t imm = SignExtend((BitExtract(opcode, 11, 8) << 1) | (BitExtract(opcode, 30, 25) << 5) |
(BitExtract(opcode, 7, 7) << 11) | (BitExtract(opcode, 31, 31) << 12), 13);
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Please check too.

// 13 | 12 1 | 0
// inst[31]/sign | inst[7] | inst[30:25] | inst[11:8] | 0
uint64_t imm = SignExtend((BitExtract(opcode, 11, 8) << 1) | (BitExtract(opcode, 30, 25) << 5) |
(BitExtract(opcode, 7, 7) << 11) | (BitExtract(opcode, 31, 31) << 12), 13);
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Please check this too.

@clamp03 clamp03 requested a review from jkotas November 15, 2023 01:16
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Thanks

@jkotas jkotas merged commit 2a9c80b into dotnet:main Nov 15, 2023
@gbalykov
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@jkotas can you please add @viewizard to .net org?

@viewizard viewizard deleted the riscv64 branch November 15, 2023 08:55
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jkotas commented Nov 15, 2023

@jkotas can you please add @viewizard to .net org?

Why is it needed?

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Why is it needed?

He's also responsible for Tizen, specifically for debugging stuff. I though that I already added him to tizen area owners, but it was not the case, so here's a PR: #94778.

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jkotas commented Nov 15, 2023

I meant - are there extra github permissions that you expect to get from dotnet org membership? What are members allowed to do that non-members cannot?

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I meant - are there extra github permissions that you expect to get from dotnet org membership? What are members allowed to do that non-members cannot?

Nothing extra. If it's the same as for non-members, then there's probably no need to add new people.

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LGTM

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5 participants