[RISC-V] Implement emulate single step feature. (#94711)

* [RISC-V] Implement emulate single step feature.

* [RISC-V] Fix clang16 build error.

Error message  /home/clamp/runtime/src/coreclr/debug/inc/riscv64/primitives.h:52:5: error: integer value -1 is outside the valid range of values [0, 255] for this enumeration type [-Wenum-constexpr-conversion]
              (CorDebugRegister)(-1), // X0 is zero register that is not a real register. We need padding here for proper mapping with ICorDebugInfo::RegNum.
              ^

* [RISC-V] Fix sign bit.

Author: viewizard

src/coreclr/clrdefinitions.cmake

@@ -14,6 +14,8 @@ elseif (CLR_CMAKE_TARGET_ARCH_ARM)
     add_definitions(-D_ARM_WORKAROUND_)
   endif (CLR_CMAKE_HOST_WIN32 AND NOT DEFINED CLR_CROSS_COMPONENTS_BUILD)
   add_definitions(-DFEATURE_EMULATE_SINGLESTEP)
+elseif (CLR_CMAKE_TARGET_ARCH_RISCV64)
+  add_definitions(-DFEATURE_EMULATE_SINGLESTEP)
 endif (CLR_CMAKE_TARGET_ARCH_ARM64)
 
 if (CLR_CMAKE_TARGET_UNIX)

src/coreclr/debug/ee/controller.cpp

@@ -3202,7 +3202,7 @@ void DebuggerController::ApplyTraceFlag(Thread *thread)
     g_pEEInterface->MarkThreadForDebugStepping(thread, true);
     LOG((LF_CORDB,LL_INFO1000, "DC::ApplyTraceFlag marked thread for debug stepping\n"));
 
-    SetSSFlag(reinterpret_cast<DT_CONTEXT *>(context) ARM_ARG(thread) ARM64_ARG(thread));
+    SetSSFlag(reinterpret_cast<DT_CONTEXT *>(context) ARM_ARG(thread) ARM64_ARG(thread) RISCV64_ARG(thread));
 }
 
 //
@@ -3239,7 +3239,7 @@ void DebuggerController::UnapplyTraceFlag(Thread *thread)
 
     // Always need to unmark for stepping
     g_pEEInterface->MarkThreadForDebugStepping(thread, false);
-    UnsetSSFlag(reinterpret_cast<DT_CONTEXT *>(context) ARM_ARG(thread) ARM64_ARG(thread));
+    UnsetSSFlag(reinterpret_cast<DT_CONTEXT *>(context) ARM_ARG(thread) ARM64_ARG(thread) RISCV64_ARG(thread));
 }
 
 void DebuggerController::EnableExceptionHook()

src/coreclr/debug/ee/debugger.cpp

@@ -15770,7 +15770,7 @@ BOOL Debugger::IsThreadContextInvalid(Thread *pThread, CONTEXT *pCtx)
     if (success)
     {
         // Check single-step flag
-        if (IsSSFlagEnabled(reinterpret_cast<DT_CONTEXT *>(pCtx) ARM_ARG(pThread) ARM64_ARG(pThread)))
+        if (IsSSFlagEnabled(reinterpret_cast<DT_CONTEXT *>(pCtx) ARM_ARG(pThread) ARM64_ARG(pThread) RISCV64_ARG(pThread)))
         {
             // Can't hijack a thread whose SS-flag is set. This could lead to races
             // with the thread taking the SS-exception.

src/coreclr/debug/ee/riscv64/primitives.cpp

@@ -12,3 +12,25 @@ void CopyREGDISPLAY(REGDISPLAY* pDst, REGDISPLAY* pSrc)
     CONTEXT tmp;
     CopyRegDisplay(pSrc, pDst, &tmp);
 }
+
+void SetSSFlag(DT_CONTEXT *, Thread *pThread)
+{
+    _ASSERTE(pThread != NULL);
+
+    pThread->EnableSingleStep();
+}
+
+void UnsetSSFlag(DT_CONTEXT *, Thread *pThread)
+{
+    _ASSERTE(pThread != NULL);
+
+    pThread->DisableSingleStep();
+}
+
+// Check if single stepping is enabled.
+bool IsSSFlagEnabled(DT_CONTEXT *, Thread *pThread)
+{
+    _ASSERTE(pThread != NULL);
+
+    return pThread->IsSingleStepEnabled();
+}

src/coreclr/debug/inc/riscv64/primitives.h

@@ -49,7 +49,7 @@ inline CORDB_ADDRESS GetPatchEndAddr(CORDB_ADDRESS patchAddr)
 
 constexpr CorDebugRegister g_JITToCorDbgReg[] =
 {
-    (CorDebugRegister)(-1), // X0 is zero register that is not a real register. We need padding here for proper mapping with ICorDebugInfo::RegNum.
+    (CorDebugRegister)(255), // X0 is zero register that is not a real register. We need padding here for proper mapping with ICorDebugInfo::RegNum.
     REGISTER_RISCV64_RA,
     REGISTER_RISCV64_SP,
     REGISTER_RISCV64_GP,
@@ -221,24 +221,15 @@ inline bool AddressIsBreakpoint(CORDB_ADDRESS_TYPE* address)
     return CORDbgGetInstruction(address) == CORDbg_BREAK_INSTRUCTION;
 }
 
-inline void SetSSFlag(DT_CONTEXT *pContext)
-{
-    // TODO-RISCV64: RISCV64 doesn't support cpsr.
-    _ASSERTE(!"unimplemented on RISCV64 yet");
-}
+class Thread;
+// Enable single stepping.
+void SetSSFlag(DT_CONTEXT *pCtx, Thread *pThread);
 
-inline void UnsetSSFlag(DT_CONTEXT *pContext)
-{
-    // TODO-RISCV64: RISCV64 doesn't support cpsr.
-    _ASSERTE(!"unimplemented on RISCV64 yet");
-}
+// Disable single stepping
+void UnsetSSFlag(DT_CONTEXT *pCtx, Thread *pThread);
 
-inline bool IsSSFlagEnabled(DT_CONTEXT * pContext)
-{
-    // TODO-RISCV64: RISCV64 doesn't support cpsr.
-    _ASSERTE(!"unimplemented on RISCV64 yet");
-    return false;
-}
+// Check if single stepping is enabled.
+bool IsSSFlagEnabled(DT_CONTEXT *pCtx, Thread *pThread);
 
 
 inline bool PRDIsEqual(PRD_TYPE p1, PRD_TYPE p2)

src/coreclr/inc/stdmacros.h

@@ -125,6 +125,20 @@
 #define NOT_LOONGARCH64_ARG(x)    , x
 #endif
 
+#ifdef TARGET_RISCV64
+#define RISCV64_FIRST_ARG(x)  x ,
+#define RISCV64_ARG(x)        , x
+#define RISCV64_ONLY(x)       x
+#define NOT_RISCV64(x)
+#define NOT_RISCV64_ARG(x)
+#else
+#define RISCV64_FIRST_ARG(x)
+#define RISCV64_ARG(x)
+#define RISCV64_ONLY(x)
+#define NOT_RISCV64(x)        x
+#define NOT_RISCV64_ARG(x)    , x
+#endif
+
 #ifdef TARGET_64BIT
 #define LOG2_PTRSIZE 3
 #else

src/coreclr/vm/CMakeLists.txt

@@ -882,6 +882,7 @@ elseif(CLR_CMAKE_TARGET_ARCH_RISCV64)
 
     set(VM_SOURCES_WKS_ARCH
         ${ARCH_SOURCES_DIR}/profiler.cpp
+        ${ARCH_SOURCES_DIR}/singlestepper.cpp
         gcinfodecoder.cpp
     )
 endif()