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[RISC-V] Increase instruction group size #88468

Merged
merged 1 commit into from
Jul 6, 2023
Merged

[RISC-V] Increase instruction group size #88468

merged 1 commit into from
Jul 6, 2023

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alpencolt
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Similar to ARM default IG size is not enough for prolog generation.
Fixes:

JIT/jit64/hfa/main/testG/hfa_nd2G_d/hfa_nd2G_d.sh
JIT/jit64/hfa/main/testG/hfa_nd2G_r/hfa_nd2G_r.sh
JIT/jit64/hfa/main/testG/hfa_sd2G_d/hfa_sd2G_d.sh
JIT/jit64/hfa/main/testG/hfa_sd2G_r/hfa_sd2G_r.sh

Part of #84834

cc @jakobbotsch @wscho77 @HJLeee @JongHeonChoi @t-mustafin @clamp03 @gbalykov

@dotnet-issue-labeler dotnet-issue-labeler bot added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Jul 6, 2023
@ghost ghost added the community-contribution Indicates that the PR has been added by a community member label Jul 6, 2023
@clamp03 clamp03 added the arch-riscv Related to the RISC-V architecture label Jul 6, 2023
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clamp03 commented Jul 6, 2023

Please add TARGET_RISCV64 to #endif // !(TARGET_ARMARCH || TARGET_LOONGARCH64) in line# 2390.

[RISC-V] Increase instruction group size
dceffbc 
Similar to ARM default IG size is not enough for prolog generation.
@alpencolt
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Please add TARGET_RISCV64 to #endif // !(TARGET_ARMARCH || TARGET_LOONGARCH64) in line# 2390.

Thanks! done

This was referenced Jul 6, 2023
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@jakobbotsch jakobbotsch merged commit d6d383e into dotnet:main Jul 6, 2023
@ghost ghost locked as resolved and limited conversation to collaborators Aug 5, 2023
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@clamp03 clamp03 clamp03 approved these changes

@jakobbotsch jakobbotsch jakobbotsch approved these changes

@gbalykov gbalykov gbalykov approved these changes

@t-mustafin t-mustafin t-mustafin approved these changes

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arch-riscv Related to the RISC-V architecture area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI community-contribution Indicates that the PR has been added by a community member
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@alpencolt @clamp03 @jakobbotsch @gbalykov @t-mustafin