[JIT] Fix test

src/coreclr/jit/codegenriscv64.cpp

@@ -5522,7 +5522,23 @@ void CodeGen::genCodeForIndir(GenTreeIndir* tree)
 //
 void CodeGen::genCodeForCpBlkHelper(GenTreeBlk* cpBlkNode)
 {
-    NYI("unimplemented on RISCV64 yet");
+    // Destination address goes in arg0, source address goes in arg1, and size goes in arg2.
+    // genConsumeBlockOp takes care of this for us.
+    genConsumeBlockOp(cpBlkNode, REG_ARG_0, REG_ARG_1, REG_ARG_2);
+
+    if (cpBlkNode->gtFlags & GTF_BLK_VOLATILE)
+    {
+        // issue a full memory barrier before a volatile CpBlk operation
+        instGen_MemoryBarrier();
+    }
+
+    genEmitHelperCall(CORINFO_HELP_MEMCPY, 0, EA_UNKNOWN);
+
+    if (cpBlkNode->gtFlags & GTF_BLK_VOLATILE)
+    {
+        // issue a INS_BARRIER_RMB after a volatile CpBlk operation
+        instGen_MemoryBarrier(BARRIER_FULL);
+    }
 }
 
 //----------------------------------------------------------------------------------

src/coreclr/jit/emitriscv64.cpp

@@ -462,8 +462,8 @@ void emitter::emitIns_I(instruction ins, emitAttr attr, ssize_t imm)
             code |= ((imm >> 20) & 0x1) << 31;
             break;
         default:
-            fprintf(stderr, "emitIns_I %llx %llx\n", ins, code);
-            unreached();
+            fprintf(stderr, "Not implemented instruction in I: 0x%x\n", code);
+            NYI_RISCV64("illegal ins within emitIns_I!");
     }
 
     instrDesc* id = emitNewInstr(attr);
@@ -511,8 +511,8 @@ void emitter::emitIns_R_I(instruction ins, emitAttr attr, regNumber reg, ssize_t
             code |= ((imm >> 20) & 0x1) << 31;
             break;
         default:
-            fprintf(stderr, "emitIns_R_I %llx %llx\n", ins, code);
-            unreached();
+            fprintf(stderr, "Not implemented instruction in R_I: 0x%x\n", code);
+            NYI_RISCV64("illegal ins within emitIns_R_I!");
             break;
     } // end switch (ins)
 
@@ -582,7 +582,8 @@ void emitter::emitIns_R_R(
         code |= (reg2 & 0x1f) << 15;
     }
     else if ((INS_fcvt_s_w <= ins && INS_fmv_w_x >= ins) || (INS_fcvt_d_w == ins || INS_fcvt_d_wu == ins) ||
-             (INS_fcvt_s_l == ins || INS_fcvt_s_lu == ins) || (INS_fmv_d_x == ins))
+             (INS_fcvt_s_l == ins || INS_fcvt_s_lu == ins) || (INS_fmv_d_x == ins) ||
+             (INS_fcvt_d_l == ins || INS_fcvt_d_lu == ins))
 
     {
         // TODO CHECK ROUNDING MODE
@@ -600,6 +601,7 @@ void emitter::emitIns_R_R(
     }
     else
     {
+        fprintf(stderr, "Not implemented instruction in R_R: 0x%x\n", code);
         NYI_RISCV64("illegal ins within emitIns_R_R!");
     }
 
@@ -649,7 +651,7 @@ void emitter::emitIns_R_R_I(
     else
     {
         fprintf(stderr, "Not implemented instruction in R_R_I: 0x%x\n", code);
-        _ASSERTE(!"TODO RISCV64 NYI");
+        NYI_RISCV64("illegal ins within emitIns_R_R_I!");
     }
     instrDesc* id = emitNewInstr(attr);
 
@@ -755,7 +757,7 @@ void emitter::emitIns_R_R_R(
     else
     {
         fprintf(stderr, "Not implemented instruction in R_R_R: 0x%x\n", code);
-        _ASSERTE(!"TODO RISCV64 NYI");
+        NYI_RISCV64("illegal ins within emitIns_R_R_R!");
     }
 
     instrDesc* id = emitNewInstr(attr);

src/coreclr/jit/instr.cpp

@@ -446,7 +446,16 @@ void CodeGen::inst_RV_RV(instruction ins,
 #ifdef TARGET_ARM
     GetEmitter()->emitIns_R_R(ins, size, reg1, reg2, flags);
 #else
-    GetEmitter()->emitIns_R_R(ins, size, reg1, reg2);
+#ifdef TARGET_RISCV64
+    if (INS_fsgnj_s == ins || INS_fsgnj_d == ins)
+    {
+        GetEmitter()->emitIns_R_R_R(ins, size, reg1, reg2, reg2);
+    }
+    else
+#endif
+    {
+        GetEmitter()->emitIns_R_R(ins, size, reg1, reg2);
+    }
 #endif
 }