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Fixes an issue with FeatureSIMD=0 and ArmBase.Yield #62351

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Merged
merged 3 commits into from
Dec 4, 2021
Merged

Fixes an issue with FeatureSIMD=0 and ArmBase.Yield #62351

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e413c0e
Mark ArmBase.Yiels with HW_Flag_NoFloatingPointUsed in src/coreclr/ji…
echesakov Dec 3, 2021
e699aa8
Move handling of ArmBase.Yield to an earlier point in impSpecialIntri…
echesakov Dec 3, 2021
3432b48
Address feedback
echesakov Dec 4, 2021
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37 changes: 18 additions & 19 deletions src/coreclr/jit/hwintrinsicarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -308,8 +308,22 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
var_types retType,
unsigned simdSize)
{
HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(intrinsic);
int numArgs = sig->numArgs;
const HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(intrinsic);
const int numArgs = sig->numArgs;

// The vast majority of "special" intrinsics are Vector64/Vector128 methods.
// The only exception is ArmBase.Yield which should be treated differently.
if (intrinsic == NI_ArmBase_Yield)
{
assert(sig->numArgs == 0);
assert(JITtype2varType(sig->retType) == TYP_VOID);
assert(simdSize == 0);

return gtNewScalarHWIntrinsicNode(TYP_VOID, intrinsic);
}

assert(category != HW_Category_Scalar);
assert(!HWIntrinsicInfo::isScalarIsa(HWIntrinsicInfo::lookupIsa(intrinsic)));

if (!featureSIMD || !IsBaselineSimdIsaSupported())
{
Expand All @@ -318,13 +332,8 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,

assert(numArgs >= 0);

var_types simdBaseType = TYP_UNKNOWN;

if (intrinsic != NI_ArmBase_Yield)
{
simdBaseType = JitType2PreciseVarType(simdBaseJitType);
assert(varTypeIsArithmetic(simdBaseType));
}
const var_types simdBaseType = JitType2PreciseVarType(simdBaseJitType);
assert(varTypeIsArithmetic(simdBaseType));

GenTree* retNode = nullptr;
GenTree* op1 = nullptr;
Expand All @@ -333,16 +342,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,

switch (intrinsic)
{
case NI_ArmBase_Yield:
{
assert(sig->numArgs == 0);
assert(JITtype2varType(sig->retType) == TYP_VOID);
assert(simdSize == 0);

retNode = gtNewScalarHWIntrinsicNode(TYP_VOID, intrinsic);
break;
}

case NI_Vector64_Abs:
case NI_Vector128_Abs:
{
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2 changes: 1 addition & 1 deletion src/coreclr/jit/hwintrinsiclistarm64.h
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Original file line number Diff line number Diff line change
Expand Up @@ -627,7 +627,7 @@ HARDWARE_INTRINSIC(Aes, PolynomialMultiplyWideningUpper,
// Base Intrinsics
HARDWARE_INTRINSIC(ArmBase, LeadingZeroCount, 0, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_clz, INS_clz, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_NoFloatingPointUsed)
HARDWARE_INTRINSIC(ArmBase, ReverseElementBits, 0, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_rbit, INS_rbit, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_NoFloatingPointUsed)
HARDWARE_INTRINSIC(ArmBase, Yield, 0, 0, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_SpecialCodeGen|HW_Flag_SpecialImport)
HARDWARE_INTRINSIC(ArmBase, Yield, 0, 0, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_NoFloatingPointUsed|HW_Flag_SpecialCodeGen|HW_Flag_SpecialImport)

// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// ISA Function name SIMD size Number of arguments Instructions Category Flags
Expand Down