PTW Hypervisor bug fixes: check GPA bits higher than HGATP.Mode

[ingallsj]

Related issue:

Type of change: bug report

Impact: functional fix

Development Phase: implementation

Release Notes

1. The PTE Cache is supposed to cache the address being requested from memory.
2. The RISC-V Privileged ISA spec states that, for every Stage-2 walk at every level of Stage-1 walk, we need to check

For Sv39x4, ... Address bits 63:41 must all be zeros, ...
For Sv48x4, ... Address bits 63:50 must all be zeros, ...
For Sv57x4, ... Address bits 63:59 must all be zeros, ...
or else a guest-page-fault exception occurs.

[sequencer]

we should add CI for Hypervisor in RocketChip. e.g. xvisor, kvm-riscv.
which testcases do you(@ingallsj @aswaterman) think, can be appropriate to add for testing?
I'll schedule someone to add these workloads.