Remove NotStrictInferReset compile option

src/main/scala/amba/axi4/UserYanker.scala

@@ -4,7 +4,6 @@ package freechips.rocketchip.amba.axi4
 
 import chisel3._
 import chisel3.util._
-import freechips.rocketchip.util.CompileOptions.NotStrictInferReset
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
@@ -74,16 +73,20 @@ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) e
       val rsel  = UIntToOH(rid,  edgeIn.master.endId).asBools
       (rqueues zip (arsel zip rsel)) foreach { case (q, (ar, r)) =>
         q.deq.ready := out.r .valid && in .r .ready && r && out.r.bits.last
+        q.deq.valid := DontCare
+        q.deq.bits := DontCare
         q.enq.valid := in .ar.valid && out.ar.ready && ar
-        q.enq.bits :<= in.ar.bits.echo
+        q.enq.ready := DontCare
+        q.enq.bits :<>= in.ar.bits.echo
+        q.count := DontCare
       }
 
       val awid = in.aw.bits.id
       val aw_ready = VecInit(wqueues.map(_.enq.ready))(awid)
       in .aw.ready := out.aw.ready && aw_ready
       out.aw.valid := in .aw.valid && aw_ready
       Connectable.waiveUnmatched(out.aw.bits, in.aw.bits) match {
-        case (lhs, rhs) => lhs :<= rhs
+        case (lhs, rhs) => lhs :<>= rhs
       }
 
       val bid = out.b.bits.id
@@ -93,14 +96,18 @@ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) e
       Connectable.waiveUnmatched(in.b, out.b) match {
         case (lhs, rhs) => lhs :<>= rhs
       }
-      in.b.bits.echo :<= b_bits
+      in.b.bits.echo :<>= b_bits
 
       val awsel = UIntToOH(awid, edgeIn.master.endId).asBools
       val bsel  = UIntToOH(bid,  edgeIn.master.endId).asBools
       (wqueues zip (awsel zip bsel)) foreach { case (q, (aw, b)) =>
         q.deq.ready := out.b .valid && in .b .ready && b
+        q.deq.valid := DontCare
+        q.deq.bits := DontCare
         q.enq.valid := in .aw.valid && out.aw.ready && aw
-        q.enq.bits :<= in.aw.bits.echo
+        q.enq.ready := DontCare
+        q.enq.bits :<>= in.aw.bits.echo
+        q.count := DontCare
       }
 
       out.w :<>= in.w

src/main/scala/devices/debug/Debug.scala

@@ -641,6 +641,9 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod
     if (supportHartArray) {
       io.innerCtrl.bits.hasel      := Mux(haselWrEn, DMCONTROLWrData.hasel, DMCONTROLReg.hasel)
       io.innerCtrl.bits.hamask     := hamask
+    } else {
+      io.innerCtrl.bits.hasel := DontCare
+      io.innerCtrl.bits.hamask := DontCare
     }
 
     io.ctrl.ndreset := DMCONTROLReg.ndmreset

src/main/scala/devices/tilelink/Plic.scala

@@ -4,7 +4,6 @@ package freechips.rocketchip.devices.tilelink
 
 import chisel3._
 import chisel3.util._
-import freechips.rocketchip.util.CompileOptions.NotStrictInferReset
 import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.diplomacy._

src/main/scala/diplomacy/LazyModule.scala

@@ -8,7 +8,6 @@ import chisel3.{Module, RawModule, Reset, withClockAndReset}
 import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord}
 import firrtl.passes.InlineAnnotation
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.util.CompileOptions.NotStrictInferReset
 
 import scala.collection.immutable.{SeqMap, SortedMap}
 import scala.util.matching._

src/main/scala/groundtest/Tile.scala

@@ -7,7 +7,7 @@ import chisel3._
 import org.chipsalliance.cde.config._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.interrupts._
-import freechips.rocketchip.rocket.{BuildHellaCache, ICacheParams, RocketCoreParams}
+import freechips.rocketchip.rocket.{BuildHellaCache, DCache, DCacheModule, ICacheParams, NonBlockingDCache, NonBlockingDCacheModule, RocketCoreParams}
 import freechips.rocketchip.tile._
 import freechips.rocketchip.tilelink._
 
@@ -40,7 +40,14 @@ abstract class GroundTestTile(
 
   val dcacheOpt = params.dcache.map { dc => LazyModule(p(BuildHellaCache)(this)(p)) }
 
-  dcacheOpt.foreach { _.hartIdSinkNodeOpt.foreach { _ := hartIdNexusNode } }
+  dcacheOpt.foreach { m =>
+    m.hartIdSinkNodeOpt.foreach { _ := hartIdNexusNode }
+    InModuleBody {
+      m.module match {
+        case module: DCacheModule => module.tlb_port := DontCare
+      }
+    }
+  }
 
   override lazy val module = new GroundTestTileModuleImp(this)
 }

src/main/scala/rocket/HellaCache.scala

@@ -269,6 +269,11 @@ trait HasHellaCache { this: BaseTile =>
   tlMasterXbar.node := dcache.node
   dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode }
   dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode }
+  InModuleBody {
+    dcache.module match {
+      case module: DCacheModule => module.tlb_port := DontCare
+    }
+  }
 }
 
 trait HasHellaCacheModule {

src/main/scala/rocket/ScratchpadSlavePort.scala

@@ -105,6 +105,7 @@ class ScratchpadSlavePort(address: Seq[AddressSet], coreDataBytes: Int, usingAto
     dmem_req_valid := (tl_in.a.valid && ready) || state === s_replay
     val dmem_req_valid_likely = (tl_in.a.valid && ready_likely) || state === s_replay
 
+    io.dmem.keep_clock_enabled := DontCare
     io.dmem.req.valid := dmem_req_valid_likely
     tl_in.a.ready := io.dmem.req.ready && ready
     io.dmem.req.bits := formCacheReq(Mux(state === s_replay, acq, tl_in.a.bits))

src/main/scala/tile/FPU.scala

@@ -5,9 +5,9 @@ package freechips.rocketchip.tile
 
 import chisel3._
 import chisel3.util._
-import freechips.rocketchip.util.CompileOptions.NotStrictInferReset
 import chisel3.{DontCare, WireInit, withClock, withReset}
 import chisel3.experimental.SourceInfo
+import chisel3.experimental.dataview._
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.rocket._
 import freechips.rocketchip.rocket.Instructions._
@@ -768,9 +768,10 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
   val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)
 
   val cp_ctrl = Wire(new FPUCtrlSigs)
-  cp_ctrl <> io.cp_req.bits
+  cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)
   io.cp_resp.valid := false.B
   io.cp_resp.bits.data := 0.U
+  io.cp_resp.bits.exc := DontCare
 
   val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)
   val mem_ctrl = RegEnable(ex_ctrl, req_valid)
@@ -822,7 +823,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
   def fuInput(minT: Option[FType]): FPInput = {
     val req = Wire(new FPInput)
     val tag = ex_ctrl.typeTagIn
-    req := ex_ctrl
+    req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)
     req.rm := ex_rm
     req.in1 := unbox(ex_rs(0), tag, minT)
     req.in2 := unbox(ex_rs(1), tag, minT)
@@ -870,7 +871,9 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
   val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))
   val divSqrt_wdata = Wire(UInt((fLen+1).W))
   val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))
-
+  divSqrt_typeTag := DontCare
+  divSqrt_wdata := DontCare
+  divSqrt_flags := DontCare
   // writeback arbitration
   case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)
   val pipes = List(

src/main/scala/tile/LazyRoCC.scala

@@ -69,6 +69,7 @@ abstract class LazyRoCC(
 
 class LazyRoCCModuleImp(outer: LazyRoCC) extends LazyModuleImp(outer) {
   val io = IO(new RoCCIO(outer.nPTWPorts, outer.roccCSRs.size))
+  io := DontCare
 }
 
 /** Mixins for including RoCC **/

src/main/scala/tile/RocketTile.scala

@@ -175,7 +175,13 @@ class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)
   // Connect the coprocessor interfaces
   if (outer.roccs.size > 0) {
     cmdRouter.get.io.in <> core.io.rocc.cmd
-    outer.roccs.foreach(_.module.io.exception := core.io.rocc.exception)
+    outer.roccs.foreach{ lm =>
+      lm.module.io.exception := core.io.rocc.exception
+      lm.module.io.fpu_req.ready := DontCare
+      lm.module.io.fpu_resp.valid := DontCare
+      lm.module.io.fpu_resp.bits.data := DontCare
+      lm.module.io.fpu_resp.bits.exc := DontCare
+    }
     core.io.rocc.resp <> respArb.get.io.out
     core.io.rocc.busy <> (cmdRouter.get.io.busy || outer.roccs.map(_.module.io.busy).reduce(_ || _))
     core.io.rocc.interrupt := outer.roccs.map(_.module.io.interrupt).reduce(_ || _)

src/main/scala/tilelink/Atomics.scala

@@ -4,8 +4,6 @@ package freechips.rocketchip.tilelink
 
 import chisel3._
 import chisel3.util._
-import freechips.rocketchip.util.CompileOptions.NotStrictInferReset
-
 
 class Atomics(params: TLBundleParameters) extends Module
 {

src/main/scala/tilelink/Broadcast.scala

@@ -4,7 +4,6 @@ package freechips.rocketchip.tilelink
 
 import chisel3._
 import chisel3.util._
-import freechips.rocketchip.util.CompileOptions.NotStrictInferReset
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper._
@@ -119,7 +118,7 @@ class TLBroadcast(params: TLBroadcastParams)(implicit p: Parameters) extends Laz
       val d_what = out.d.bits.source(d_high+1, d_high)
       val d_drop = d_what === DROP
       val d_hasData = edgeOut.hasData(out.d.bits)
-      val d_normal = Wire(in.d)
+      val d_normal = Wire(chiselTypeOf(in.d))
       val (d_first, d_last, _) = edgeIn.firstlast(d_normal)
       val d_trackerOH = VecInit(trackers.map { t => t.need_d && t.source === d_normal.bits.source }).asUInt holdUnless d_first
 
@@ -179,8 +178,8 @@ class TLBroadcast(params: TLBroadcastParams)(implicit p: Parameters) extends Laz
           in.c.bits.param === TLPermissions.BtoB)
       }
 
-      val releaseack = Wire(in.d)
-      val putfull = Wire(out.a)
+      val releaseack = Wire(chiselTypeOf(in.d))
+      val putfull = Wire(chiselTypeOf(out.a))
 
       in.c.ready := c_probeack || Mux(c_release, releaseack.ready, putfull.ready)
 

src/main/scala/util/AsyncResetReg.scala

@@ -2,8 +2,6 @@
 
 package freechips.rocketchip.util
 
-import freechips.rocketchip.util.CompileOptions.NotStrictInferReset
-
 import chisel3._
 
 /** This black-boxes an Async Reset