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CSR mcountinhibit #2693

Merged
merged 3 commits into from
Nov 3, 2020
Merged

CSR mcountinhibit #2693

merged 3 commits into from
Nov 3, 2020

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ingallsj
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Related issue:

Type of change: feature request

Impact: API addition (no impact on existing code)

Development Phase: implementation

Release Notes
add CSR mcountinhibit as was defined in RISC-V Privileged ISA version 1.11

@ingallsj
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ingallsj commented Oct 30, 2020

Questions / discussion points:

  • I instantiated reg_mcountinhibit as a RegInit with reset to zero, to maintain compatibility with software that might not initialize this CSR. Could we save some fanout on the reset by instantiating reg_mcountinhibit as a plain Reg?

  • I instantiated reg_mcountinhibit unconditionally. Should I make it conditional on a parameter, such as coreParams.haveCounterInhibit?

  • I changed reg_cycle to be inhibited by reg_mcountinhibit(0) for both options of parameter if (enableCommitLog). Should I have kept that as if (enableCommitLog) reg_instret?

@aswaterman
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My sense is that in this case we should cope with the slightly higher reset fanout to avoid the PITA for software.

I think instantiating it unconditionally is OK, since it's just 1 flop per relatively expensive counter.

I'm not certain what the right thing to do for enableCommitLog is, but my sense is that what you did is best. Certainly the HW cost is not a concern, since it's not meant to be used in production.

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LGTM minor the one nit.

@ingallsj ingallsj merged commit 2040099 into master Nov 3, 2020
@ingallsj ingallsj deleted the mcountinhibit branch November 3, 2020 01:03
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