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Misc. fixes to make Rocket tolerant to X-propagation #2659

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merged 9 commits into from
Oct 12, 2020
Merged

Misc. fixes to make Rocket tolerant to X-propagation #2659

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41313ac
Reset RAS pointers because of X-pessimism
aswaterman Oct 9, 2020
338670d
Add state machine to initialize BHT because of X-pessimism
aswaterman Oct 9, 2020
bf630c1
Make BTB X-tolerant
aswaterman Oct 9, 2020
20655ee
Make D$ X-tolerant
aswaterman Oct 9, 2020
3daa127
Fix an X-pessimism problem in the Frontend
aswaterman Oct 9, 2020
5908fe0
Fix a truly preposterous X-pessimism problem
aswaterman Oct 9, 2020
1b5e88b
Work aroud Verilog idiocy that (0 << 'x) is 'x
aswaterman Oct 9, 2020
f7b1977
Initialize pLRU state for X-tolerance
aswaterman Oct 9, 2020
60d8c98
bump hardfloat for X-propagation fix
aswaterman Oct 9, 2020
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Work aroud Verilog idiocy that (0 << 'x) is 'x
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@aswaterman
aswaterman committed Oct 10, 2020
commit 1b5e88b16bc1f2e615ed7381f6662b7bc999399d
4 changes: 2 additions & 2 deletions src/main/scala/util/IDPool.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -22,8 +22,8 @@ class IDPool(numIds: Int) extends Module {
io.alloc.valid := valid
io.alloc.bits := select

val taken = (io.alloc.ready << io.alloc.bits)(numIds-1, 0)
val given = (io.free .valid << io.free .bits)(numIds-1, 0)
val taken = Mux(io.alloc.ready, (1.U << io.alloc.bits)(numIds-1, 0), 0.U)
val given = Mux(io.free .valid, (1.U << io.free .bits)(numIds-1, 0), 0.U)
val bitmap1 = (bitmap & ~taken) | given
val select1 = OHToUInt(~(leftOR(bitmap1, numIds) << 1) & bitmap1, numIds)
val valid1 = bitmap1.orR
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