remove EnhancedChisel3Assign (#3451)

* remove EnhancedChisel3Assign in AHBLite

* remove EnhancedChisel3Assign in AHBXBar

* remove EnhancedChisel3Assign in APBXBar

* remove EnhancedChisel3Assign in AXI4CreditedBuffer

* remove EnhancedChisel3Assign in Deinterleaver.scala

* remove EnhancedChisel3Assign in AXI4Filter

* remove EnhancedChisel3Assign in AXI4Fragmenter.scala

* remove EnhancedChisel3Assign in AXI4IdIndexer

* remove EnhancedChisel3Assign in AXI4RegisterNode

* remove EnhancedChisel3Assign in AXI4ToTL

* remove EnhancedChisel3Assign in AXI4UserYanker

* remove EnhancedChisel3Assign in AXI4Xbar

* remove EnhancedChisel3Assign in AXISBuffer

* remove EnhancedChisel3Assign in AXISXBar

* remove EnhancedChisel3Assign in RegisterRouter

* remove EnhancedChisel3Assign in tilelink AddressAdjuster

* remove EnhancedChisel3Assign in tilelink Arbiter

* remove EnhancedChisel3Assign in tilelink BlockDuringReset

* remove EnhancedChisel3Assign in tilelink Credited

* remove EnhancedChisel3Assign in tilelink Fragmenter

* remove EnhancedChisel3Assign in tilelink HintHandler

* remove EnhancedChisel3Assign in tilelink RegisterRouter

* remove EnhancedChisel3Assign in tilelink ToAHB

* remove EnhancedChisel3Assign in tilelink ToAPB

* remove EnhancedChisel3Assign in tilelink ToAXI4

* fix: replace with connectable API

* fix: replace with connectable API

* fix: bad connection between `ar` channels

* fix: remove `DontCare` with no effect

* remove EnhancedChisel3Assign

---------

Co-authored-by: Takehana <cowpowermax@pm.me>

src/main/scala/amba/ahb/AHBLite.scala

@@ -5,7 +5,6 @@ package freechips.rocketchip.amba.ahb
 import chisel3._
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.util.EnhancedChisel3Assign
 
 class AHBLite()(implicit p: Parameters) extends LazyModule {
   val node = AHBMasterAdapterNode(
@@ -29,8 +28,8 @@ class AHBLite()(implicit p: Parameters) extends LazyModule {
       out.hprot  := in.hprot
       out.haddr  := in.haddr
       out.hwdata := in.hwdata
-      out.hauser :<> in.hauser
-      in.hduser :<> out.hduser
+      out.hauser :<>= in.hauser
+      in.hduser :<>= out.hduser
       in.hrdata := out.hrdata
     }
   }

src/main/scala/amba/ahb/Xbar.scala

@@ -7,7 +7,6 @@ import chisel3.util._
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
-import freechips.rocketchip.util.EnhancedChisel3Assign
 
 class AHBFanout()(implicit p: Parameters) extends LazyModule {
   val node = new AHBFanoutNode(
@@ -47,7 +46,7 @@ class AHBFanout()(implicit p: Parameters) extends LazyModule {
 
       when (in.hready) { d_sel := a_sel }
       (a_sel zip io_out) foreach { case (sel, out) =>
-        out :<> in
+        out :<>= in
         out.hsel := in.hsel && sel
         out.hmaster.map { _ := 0.U }
       }

src/main/scala/amba/apb/Xbar.scala

@@ -7,7 +7,6 @@ import chisel3.util._
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
-import freechips.rocketchip.util.EnhancedChisel3Assign
 
 class APBFanout()(implicit p: Parameters) extends LazyModule {
   val node = new APBNexusNode(
@@ -44,7 +43,7 @@ class APBFanout()(implicit p: Parameters) extends LazyModule {
 
       val sel = VecInit(route_addrs.map(seq => seq.map(_.contains(in.paddr)).reduce(_ || _)))
       (sel zip io_out) foreach { case (sel, out) =>
-        out :<> in
+        out :<>= in
         out.psel    := sel && in.psel
         out.penable := sel && in.penable
       }

src/main/scala/amba/axi4/Credited.scala

@@ -8,7 +8,6 @@ import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.subsystem.CrossingWrapper
 import freechips.rocketchip.util._
-import freechips.rocketchip.util.EnhancedChisel3Assign
 
 class AXI4CreditedBuffer(delay: AXI4CreditedDelay)(implicit p: Parameters) extends LazyModule
 {
@@ -19,11 +18,11 @@ class AXI4CreditedBuffer(delay: AXI4CreditedDelay)(implicit p: Parameters) exten
   lazy val module = new Impl
   class Impl extends LazyModuleImp(this) {
     (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
-      out.aw :<> in.aw.pipeline(delay.aw)
-      out.w :<> in.w.pipeline(delay.w)
-      in.b :<> out.b.pipeline(delay.b)
-      out.ar :<> in.ar.pipeline(delay.ar)
-      in.r :<> out.r.pipeline(delay.r)
+      out.aw :<>= in.aw.pipeline(delay.aw)
+      out.w :<>= in.w.pipeline(delay.w)
+      in.b :<>= out.b.pipeline(delay.b)
+      out.ar :<>= in.ar.pipeline(delay.ar)
+      in.r :<>= out.r.pipeline(delay.r)
     }
   }
 }
@@ -44,11 +43,11 @@ class AXI4CreditedSource(delay: AXI4CreditedDelay)(implicit p: Parameters) exten
   class Impl extends LazyModuleImp(this) {
     (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
       val tld = edgeOut.delay
-      out.aw :<> CreditedIO.fromSender(in.aw, tld.aw.total).pipeline(delay.aw)
-      out.w :<> CreditedIO.fromSender(in.w, tld.w.total).pipeline(delay.w)
-      in.b :<> out.b.pipeline(delay.b).toReceiver(tld.b.total)
-      out.ar :<> CreditedIO.fromSender(in.ar, tld.ar.total).pipeline(delay.ar)
-      in.r :<> out.r.pipeline(delay.r).toReceiver(tld.r.total)
+      out.aw :<>= CreditedIO.fromSender(in.aw, tld.aw.total).pipeline(delay.aw)
+      out.w :<>= CreditedIO.fromSender(in.w, tld.w.total).pipeline(delay.w)
+      in.b :<>= out.b.pipeline(delay.b).toReceiver(tld.b.total)
+      out.ar :<>= CreditedIO.fromSender(in.ar, tld.ar.total).pipeline(delay.ar)
+      in.r :<>= out.r.pipeline(delay.r).toReceiver(tld.r.total)
     }
   }
 }
@@ -69,11 +68,11 @@ class AXI4CreditedSink(delay: AXI4CreditedDelay)(implicit p: Parameters) extends
   class Impl extends LazyModuleImp(this) {
     (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
       val tld = edgeIn.delay
-      out.aw :<> in.aw.pipeline(delay.aw).toReceiver(tld.aw.total)
-      out.w :<> in.w.pipeline(delay.w).toReceiver(tld.w.total)
-      in.b :<> CreditedIO.fromSender(out.b, tld.b.total).pipeline(delay.b)
-      out.ar :<> in.ar.pipeline(delay.ar).toReceiver(tld.ar.total)
-      in.r :<> CreditedIO.fromSender(out.r, tld.r.total).pipeline(delay.r)
+      out.aw :<>= in.aw.pipeline(delay.aw).toReceiver(tld.aw.total)
+      out.w :<>= in.w.pipeline(delay.w).toReceiver(tld.w.total)
+      in.b :<>= CreditedIO.fromSender(out.b, tld.b.total).pipeline(delay.b)
+      out.ar :<>= in.ar.pipeline(delay.ar).toReceiver(tld.ar.total)
+      in.r :<>= CreditedIO.fromSender(out.r, tld.r.total).pipeline(delay.r)
     }
   }
 }

src/main/scala/amba/axi4/Deinterleaver.scala

@@ -8,7 +8,6 @@ import chisel3.util.{Cat, isPow2, log2Ceil, ReadyValidIO,
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util.leftOR
-import freechips.rocketchip.util.EnhancedChisel3Assign
 
 /** This adapter deinterleaves read responses on the R channel.
   *
@@ -48,14 +47,14 @@ class AXI4Deinterleaver(maxReadBytes: Int, buffer: BufferParams = BufferParams.d
       val beats = maxBeats(edgeOut.slave)
 
       // This adapter passes through the AR/AW control + W/B write data channels
-      out.ar :<> in.ar
-      out.aw :<> in.aw
-      out.w :<> in.w
-      in.b :<> out.b
+      out.ar :<>= in.ar
+      out.aw :<>= in.aw
+      out.w :<>= in.w
+      in.b :<>= out.b
 
       // Only the R channel has the possibility of being changed
       if (nothingToDeinterleave(edgeOut.slave)) {
-        in.r.asInstanceOf[ReadyValidIO[AXI4BundleR]] :<> buffer.irrevocable(out.r)
+        in.r.asInstanceOf[ReadyValidIO[AXI4BundleR]] :<>= buffer.irrevocable(out.r)
       } else {
         // We only care to deinterleave ids that are actually in use
         val maxFlightPerId = Seq.tabulate(endId) { i =>

src/main/scala/amba/axi4/Filter.scala

@@ -4,7 +4,6 @@ package freechips.rocketchip.amba.axi4
 
 import org.chipsalliance.cde.config._
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.util.EnhancedChisel3Assign
 
 class AXI4Filter(
   Sfilter: AXI4SlaveParameters  => Option[AXI4SlaveParameters]   = AXI4Filter.Sidentity,
@@ -33,7 +32,7 @@ class AXI4Filter(
   lazy val module = new Impl
   class Impl extends LazyModuleImp(this) {
     (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
-      out :<> in
+      out :<>= in
     }
   }
 }

src/main/scala/amba/axi4/Fragmenter.scala

@@ -7,7 +7,6 @@ import chisel3.util._
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
-import freechips.rocketchip.util.EnhancedChisel3Assign
 
 case object AXI4FragLast extends ControlKey[Bool]("real_last")
 case class AXI4FragLastField() extends SimpleBundleField(AXI4FragLast)(Output(Bool()), false.B)
@@ -148,7 +147,9 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
       val in_w = Queue.irrevocable(in.w, 1, flow=true)
 
       // AR flow control; super easy
-      out.ar :<>: in_ar
+      Connectable.waiveUnmatched(out.ar, in_ar) match {
+        case (lhs, rhs) => lhs :<>= rhs
+      }
       out.ar.bits.echo(AXI4FragLast) := ar_last
 
       // When does W channel start counting a new transfer
@@ -162,7 +163,9 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
       out.aw.valid := in_aw.valid && (wbeats_ready || wbeats_latched)
       in_aw.ready := out.aw.ready && (wbeats_ready || wbeats_latched)
       wbeats_valid := in_aw.valid && !wbeats_latched
-      out.aw.bits :<>: in_aw.bits
+      Connectable.waiveUnmatched(out.aw.bits, in_aw.bits) match {
+        case (lhs, rhs) => lhs :<>= rhs
+      }
       out.aw.bits.echo(AXI4FragLast) := aw_last
 
       // We need to inject 'last' into the W channel fragments, count!
@@ -184,12 +187,19 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
 
       // R flow control
       val r_last = out.r.bits.echo(AXI4FragLast)
-      in.r :<> out.r
+      Connectable.waiveUnmatched(in.r, out.r) match {
+        case (lhs, rhs) => lhs :<>= rhs
+      }
+
       in.r.bits.last := out.r.bits.last && r_last
 
       // B flow control
       val b_last = out.b.bits.echo(AXI4FragLast)
-      in.b :<> out.b
+
+      Connectable.waiveUnmatched(in.b, out.b) match {
+        case (lhs, rhs) => lhs :<>= rhs
+      }
+
       in.b.valid := out.b.valid && b_last
       out.b.ready := in.b.ready || !b_last
 

src/main/scala/amba/axi4/IdIndexer.scala

@@ -7,7 +7,6 @@ import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
 import chisel3.util.{log2Ceil, Cat}
-import freechips.rocketchip.util.EnhancedChisel3Assign
 
 case object AXI4ExtraId extends ControlKey[UInt]("extra_id")
 case class AXI4ExtraIdField(width: Int) extends SimpleBundleField(AXI4ExtraId)(Output(UInt(width.W)), 0.U)
@@ -61,11 +60,22 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule
     (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
 
       // Leave everything mostly untouched
-      out.ar :<> in.ar
-      out.aw :<> in.aw
-      out.w :<> in.w
-      in.b :<> out.b
-      in.r :<> out.r
+
+      Connectable.waiveUnmatched(out.ar, in.ar) match {
+        case (lhs, rhs) => lhs.squeezeAll :<>= rhs.squeezeAll
+      }
+      Connectable.waiveUnmatched(out.aw, in.aw) match {
+        case (lhs, rhs) => lhs.squeezeAll :<>= rhs.squeezeAll
+      }
+      Connectable.waiveUnmatched(out.w, in.w) match {
+        case (lhs, rhs) => lhs.squeezeAll :<>= rhs.squeezeAll
+      }
+      Connectable.waiveUnmatched(in.b, out.b) match {
+        case (lhs, rhs) => lhs.squeezeAll :<>= rhs.squeezeAll
+      }
+      Connectable.waiveUnmatched(in.r, out.r) match {
+        case (lhs, rhs) => lhs.squeezeAll :<>= rhs.squeezeAll
+      }
 
       val bits = log2Ceil(edgeIn.master.endId) - idBits
       if (bits > 0) {

src/main/scala/amba/axi4/RegisterRouter.scala

@@ -48,8 +48,8 @@ case class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes
     aw.ready := in.ready && !ar.valid && w .valid
     w .ready := in.ready && !ar.valid && aw.valid
 
-    ar_extra.partialAssignL(ar.bits.echo)
-    aw_extra.partialAssignL(aw.bits.echo)
+    ar_extra :<= ar.bits.echo
+    aw_extra :<= aw.bits.echo
     ar_extra(AXI4RRId) := ar.bits.id
     aw_extra(AXI4RRId) := aw.bits.id
     val addr = Mux(ar.valid, ar.bits.addr, aw.bits.addr)

src/main/scala/amba/axi4/ToTL.scala

@@ -9,7 +9,6 @@ import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
-import freechips.rocketchip.util.EnhancedChisel3Assign
 
 case class AXI4ToTLIdMapEntry(tlId: IdRange, axi4Id: IdRange, name: String)
   extends IdMapEntry
@@ -111,7 +110,10 @@ class AXI4ToTL(wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule
       r_out.valid := in.ar.valid
       r_out.bits :<= edgeOut.Get(r_id, r_addr, r_size)._2
 
-      r_out.bits.user :<= in.ar.bits.user
+      Connectable.waiveUnmatched(r_out.bits.user, in.ar.bits.user) match {
+        case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll
+      }
+
       r_out.bits.user.lift(AMBAProt).foreach { rprot =>
         rprot.privileged :=  in.ar.bits.prot(0)
         rprot.secure     := !in.ar.bits.prot(1)
@@ -147,7 +149,10 @@ class AXI4ToTL(wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule
       w_out.bits :<= edgeOut.Put(w_id, w_addr, w_size, in.w.bits.data, in.w.bits.strb)._2
       in.w.bits.user.lift(AMBACorrupt).foreach { w_out.bits.corrupt := _ }
 
-      w_out.bits.user :<= in.aw.bits.user
+      Connectable.waiveUnmatched(w_out.bits.user, in.aw.bits.user) match {
+        case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll
+      }
+
       w_out.bits.user.lift(AMBAProt).foreach { wprot =>
         wprot.privileged :=  in.aw.bits.prot(0)
         wprot.secure     := !in.aw.bits.prot(1)
@@ -183,7 +188,7 @@ class AXI4ToTL(wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule
       ok_r.bits.user :<= out.d.bits.user
 
       // AXI4 needs irrevocable behaviour
-      in.r :<> Queue.irrevocable(ok_r, 1, flow=true)
+      in.r :<>= Queue.irrevocable(ok_r, 1, flow=true)
 
       ok_b.bits.id   := out.d.bits.source >> addedBits
       ok_b.bits.resp := d_resp

src/main/scala/amba/axi4/UserYanker.scala

@@ -8,7 +8,6 @@ import freechips.rocketchip.util.CompileOptions.NotStrictInferReset
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
-import freechips.rocketchip.util.EnhancedChisel3Assign
 
 /** This adapter prunes all user bit fields of the echo type from request messages,
   * storing them in queues and echoing them back when matching response messages are received.
@@ -58,13 +57,17 @@ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) e
       val ar_ready = VecInit(rqueues.map(_.enq.ready))(arid)
       in .ar.ready := out.ar.ready && ar_ready
       out.ar.valid := in .ar.valid && ar_ready
-      out.ar.bits :<= in .ar.bits
+      Connectable.waiveUnmatched(out.ar.bits, in.ar.bits) match {
+        case (lhs, rhs) => lhs :<= rhs
+      }
 
       val rid = out.r.bits.id
       val r_valid = VecInit(rqueues.map(_.deq.valid))(rid)
       val r_bits = VecInit(rqueues.map(_.deq.bits))(rid)
       assert (!out.r.valid || r_valid) // Q must be ready faster than the response
-      in.r :<> out.r
+      Connectable.waiveUnmatched(in.r, out.r) match {
+        case (lhs, rhs) => lhs :<>= rhs
+      }
       in.r.bits.echo :<= r_bits
 
       val arsel = UIntToOH(arid, edgeIn.master.endId).asBools
@@ -79,13 +82,17 @@ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) e
       val aw_ready = VecInit(wqueues.map(_.enq.ready))(awid)
       in .aw.ready := out.aw.ready && aw_ready
       out.aw.valid := in .aw.valid && aw_ready
-      out.aw.bits :<= in .aw.bits
+      Connectable.waiveUnmatched(out.aw.bits, in.aw.bits) match {
+        case (lhs, rhs) => lhs :<= rhs
+      }
 
       val bid = out.b.bits.id
       val b_valid = VecInit(wqueues.map(_.deq.valid))(bid)
       val b_bits = VecInit(wqueues.map(_.deq.bits))(bid)
       assert (!out.b.valid || b_valid) // Q must be ready faster than the response
-      in.b :<> out.b
+      Connectable.waiveUnmatched(in.b, out.b) match {
+        case (lhs, rhs) => lhs :<>= rhs
+      }
       in.b.bits.echo :<= b_bits
 
       val awsel = UIntToOH(awid, edgeIn.master.endId).asBools
@@ -96,7 +103,7 @@ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) e
         q.enq.bits :<= in.aw.bits.echo
       }
 
-      out.w :<> in.w
+      out.w :<>= in.w
     }
   }
 }

src/main/scala/amba/axi4/Xbar.scala

@@ -9,7 +9,6 @@ import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
 import freechips.rocketchip.unittest._
 import freechips.rocketchip.tilelink._
-import freechips.rocketchip.util.EnhancedChisel3Assign
 
 /**
   * AXI4 Crossbar. It connects multiple AXI4 masters to slaves.
@@ -86,7 +85,7 @@ class AXI4Xbar(
     // Transform input bundles
     val in = Wire(Vec(io_in.size, new AXI4Bundle(wide_bundle)))
     for (i <- 0 until in.size) {
-      in(i) :<> io_in(i)
+      in(i) :<>= io_in(i)
 
       // Handle size = 1 gracefully (Chisel3 empty range is broken)
       def trim(id: UInt, size: Int) = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
@@ -169,7 +168,7 @@ class AXI4Xbar(
     // Transform output bundles
     val out = Wire(Vec(io_out.size, new AXI4Bundle(wide_bundle)))
     for (i <- 0 until out.size) {
-      io_out(i) :<> out(i)
+      io_out(i) :<>= out(i)
 
       if (io_in.size > 1) {
         // Block AW if we cannot record the W source

src/main/scala/amba/axis/Buffer.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.amba.axis
 
 import org.chipsalliance.cde.config._
-import freechips.rocketchip.util._
 import freechips.rocketchip.diplomacy._
 
 class AXISBuffer(val params: BufferParams)(implicit p: Parameters) extends LazyModule
@@ -12,7 +11,7 @@ class AXISBuffer(val params: BufferParams)(implicit p: Parameters) extends LazyM
   lazy val module = new Impl
   class Impl extends LazyModuleImp(this) {
     (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
-      out :<>: params.irrevocable(in)
+      out.waiveAs[chisel3.Data]() :<>= params.irrevocable(in).waiveAs[chisel3.Data]()
     }
   }
 }