D$: prefer replacing into invalid ways within a set

This would only matter after a cache flush for single-core designs, but
for multicore designs, the benefit can matter after write-sharing, too.

src/main/scala/rocket/DCache.scala

@@ -395,7 +395,11 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   val s2_cannot_victimize = !s2_flush_valid && io.cpu.s2_kill
   val s2_victimize = s2_want_victimize && !s2_cannot_victimize
   val s2_valid_uncached_pending = s2_valid_miss && s2_uncached && !uncachedInFlight.asUInt.andR
-  val s2_victim_way = UIntToOH(RegEnable(s1_victim_way, s1_valid_not_nacked || s1_flush_valid))
+  val s2_victim_way = {
+    val common_case = UIntToOH(RegEnable(s1_victim_way, s1_valid_not_nacked || s1_flush_valid))
+    val invalids = s2_meta_corrected.map(_.coh === ClientMetadata.onReset)
+    Mux(invalids.orR, PriorityEncoder(invalids), common_case)
+  }
   val s2_victim_or_hit_way = Mux(s2_hit_valid, s2_hit_way, s2_victim_way)
   val s2_victim_tag = Mux(s2_valid_data_error || s2_valid_flush_line, s2_req.addr(paddrBits-1, tagLSB), Mux1H(s2_victim_way, s2_meta_corrected).tag)
   val s2_victim_state = Mux(s2_hit_valid, s2_hit_state, Mux1H(s2_victim_way, s2_meta_corrected).coh)