Add seipNode similar to meipNode

chipsalliance · Oct 13, 2020 · 01fd55d · 01fd55d
1 parent 5c0c935
commit 01fd55d
Showing 1 changed file with 15 additions and 1 deletion.
diff --git a/src/main/scala/subsystem/HasTiles.scala b/src/main/scala/subsystem/HasTiles.scala
@@ -114,6 +114,14 @@ trait HasTileInterruptSources
       outputRequiresInput = false,
       inputRequiresOutput = false))
   }
+  val seipNode = p(PLICKey) match {
+    case Some(_) => None
+    case None    => Some(IntNexusNode(
+      sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1))) },
+      sinkFn   = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
+      outputRequiresInput = false,
+      inputRequiresOutput = false))
+  }
 }
 
 /** These are sources of "constants" that are driven into the tile.
@@ -297,7 +305,7 @@ trait CanAttachTile {
     if (domain.tile.tileParams.core.hasSupervisorMode) {
       domain.crossIntIn(crossingParams.crossingType) :=
         context.plicOpt .map { _.intnode }
-          .getOrElse { NullIntSource() }
+          .getOrElse { context.seipNode.get }
     }
 
     // 3. Local Interrupts ("lip") are required to already be synchronous to the Tile's clock.
@@ -404,4 +412,10 @@ trait HasTilesModuleImp extends LazyModuleImp with HasPeripheryDebugModuleImp {
       (outer.meipNode.get.out(i)._1)(0) := pin
     }
   }
+  val seip = if(outer.seipNode.isDefined) Some(IO(Vec(outer.seipNode.get.out.size, Bool()).asInput)) else None
+  seip.foreach { s =>
+    s.zipWithIndex.foreach{ case (pin, i) =>
+      (outer.seipNode.get.out(i)._1)(0) := pin
+    }
+  }
 }