DeadCodeElimination transform is not working properly.

[poddar92]

Checklist

• [ y] Did you specify the current behavior?
• [y ] Did you specify the expected behavior?
• [ y] Did you provide a code example showing the problem?
• [ y] Did you describe your environment?
• [ N/A] Did you specify relevant external information?

What is the current behavior?

Currently; it is removing some nodes from a module; but those nodes are still being used fro other purposes. It is either not cleaning up the whole node chain or it is removing undesired nodes (which are not dead)

example module dumps (firrtl circuit) before and after running DCE
circuitOld.log
circuitNew.log
DCEDebug.log

before circuit module: circuitOld file
After DCE run module definition (firrtl circuit): circuitNew file
The DCEDebug log for the module is also attached.

A little about the module: We have added a transform to insert RAS for all registers. the deleted nodes in question are for that new logic. (you can look for example of node parityreg_clock_4; check_clock_4 which ultimately connects to ras_error.

I could not work on a simple testcase to reproduce this issue. Hopefully this information helps.

What is the expected behavior?

One of the deleted nodes (highlighted above) is coming from primary input to the module (io_enq_bits_data[255:0]) which is not optimized by DCE. This node should not have been deleted as the final output (ras_error) is also not optimized by DCE.

Steps to Reproduce

I could not get to work on the smaller testcase for this failure. I can provide stack trace if that would help.

Exception in thread "main" firrtl.FirrtlInternalException: Internal Error! Please file an issue at https://github.com/ucb-bar/firrtl/issues
	at firrtl.Utils$.error(Utils.scala:471)
	at firrtl.Utils$.throwInternalError(Utils.scala:175)
	at firrtl.stage.phases.CatchExceptions.transform(CatchExceptions.scala:31)
	at firrtl.stage.phases.CatchExceptions.transform(CatchExceptions.scala:10)
	at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
	at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
	at firrtl.options.Translator.transform(Phase.scala:248)
	at firrtl.options.Translator.transform$(Phase.scala:248)
	at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
	at firrtl.options.DependencyManager.$anonfun$transform$5(DependencyManager.scala:280)
	at firrtl.Utils$.time(Utils.scala:181)
	at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:280)
	at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)
	at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)
	at scala.collection.immutable.List.foldLeft(List.scala:89)
	at firrtl.options.DependencyManager.transform(DependencyManager.scala:269)
	at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255)
	at firrtl.options.PhaseManager.transform(DependencyManager.scala:443)
	at firrtl.stage.FirrtlStage.run(FirrtlStage.scala:38)
	at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
	at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
	at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
	at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
	at firrtl.options.Translator.transform(Phase.scala:248)
	at firrtl.options.Translator.transform$(Phase.scala:248)
	at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
	at firrtl.options.Stage.$anonfun$transform$5(Stage.scala:47)
	at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)
	at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)
	at scala.collection.immutable.List.foldLeft(List.scala:89)
	at firrtl.options.Stage.$anonfun$transform$3(Stage.scala:47)
	at logger.Logger$.$anonfun$makeScope$2(Logger.scala:137)
	at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)
	at logger.Logger$.makeScope(Logger.scala:135)
	at firrtl.options.Stage.transform(Stage.scala:47)
	at firrtl.options.Stage.execute(Stage.scala:58)
	at firrtl.options.StageMain.main(Stage.scala:71)
	at firrtl.stage.FirrtlMain.main(FirrtlStage.scala)
Caused by: java.util.NoSuchElementException: key not found: check_clock_4
	at scala.collection.MapLike.default(MapLike.scala:235)
	at scala.collection.MapLike.default$(MapLike.scala:234)
	at scala.collection.AbstractMap.default(Map.scala:63)
	at scala.collection.mutable.HashMap.apply(HashMap.scala:69)
	at firrtl.passes.ResolveKinds$.resolve_expr(ResolveKinds.scala:24)
	at firrtl.passes.ResolveKinds$.$anonfun$resolve_expr$1(ResolveKinds.scala:25)
	at scala.collection.immutable.Stream.$anonfun$map$1(Stream.scala:418)
	at scala.collection.immutable.Stream$Cons.tail(Stream.scala:1171)
	at scala.collection.immutable.Stream$Cons.tail(Stream.scala:1161)
	at scala.collection.immutable.StreamIterator.$anonfun$next$1(Stream.scala:1061)
	at scala.collection.immutable.StreamIterator$LazyCell.v$lzycompute(Stream.scala:1050)
	at scala.collection.immutable.StreamIterator$LazyCell.v(Stream.scala:1050)
	at scala.collection.immutable.StreamIterator.hasNext(Stream.scala:1055)
	at firrtl.ir.Serializer$.s(Serializer.scala:300)
	at firrtl.ir.Serializer$.s(Serializer.scala:74)
	at firrtl.ir.Serializer$.s(Serializer.scala:96)
	at firrtl.ir.Serializer$.s(Serializer.scala:110)
	at firrtl.ir.Serializer$.s(Serializer.scala:246)
	at firrtl.ir.Serializer$.$anonfun$s$9(Serializer.scala:260)
	at firrtl.ir.Serializer$.$anonfun$s$9$adapted(Serializer.scala:260)
	at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:62)
	at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:55)
	at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:49)
	at firrtl.ir.Serializer$.s(Serializer.scala:260)
	at firrtl.ir.Serializer$.serialize(Serializer.scala:36)
	at firrtl.ir.Serializer$.serialize(Serializer.scala:17)
	at firrtl.ir.UseSerializer.serialize(IR.scala:22)
	at firrtl.ir.UseSerializer.serialize$(IR.scala:22)
	at firrtl.ir.Circuit.serialize(IR.scala:1231)
	at firrtl.Transform$.$anonfun$remapAnnotations$3(Compiler.scala:221)
	at logger.Logger$.logIt$1(Logger.scala:203)
	at logger.Logger$.logger$Logger$$showMessage(Logger.scala:211)
	at logger.Logger.trace(Logger.scala:389)
	at firrtl.Transform$.remapAnnotations(Compiler.scala:221)
	at firrtl.stage.transforms.UpdateAnnotations.bToA(UpdateAnnotations.scala:18)
	at firrtl.stage.transforms.UpdateAnnotations.bToA(UpdateAnnotations.scala:8)
	at firrtl.options.Translator.transform(Phase.scala:248)
	at firrtl.options.Translator.transform$(Phase.scala:248)
	at firrtl.stage.transforms.UpdateAnnotations.transform(UpdateAnnotations.scala:8)
	at firrtl.options.DependencyManager.$anonfun$transform$5(DependencyManager.scala:280)
	at firrtl.Utils$.time(Utils.scala:181)
	at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:280)
	at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)
	at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)
	at scala.collection.immutable.List.foldLeft(List.scala:89)
	at firrtl.options.DependencyManager.transform(DependencyManager.scala:269)
	at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255)
	at firrtl.stage.TransformManager.transform(TransformManager.scala:14)
	at firrtl.stage.phases.Compiler.$anonfun$internalTransform$6(Compiler.scala:138)
	at firrtl.Utils$.time(Utils.scala:181)
	at firrtl.stage.phases.Compiler.f$1(Compiler.scala:138)
	at firrtl.stage.phases.Compiler.$anonfun$internalTransform$8(Compiler.scala:143)
	at scala.collection.TraversableLike.$anonfun$map$1(TraversableLike.scala:238)
	at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:62)
	at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:55)
	at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:49)
	at scala.collection.TraversableLike.map(TraversableLike.scala:238)
	at scala.collection.TraversableLike.map$(TraversableLike.scala:231)
	at scala.collection.AbstractTraversable.map(Traversable.scala:108)
	at firrtl.stage.phases.Compiler.internalTransform(Compiler.scala:143)
	at firrtl.stage.phases.Compiler.internalTransform(Compiler.scala:53)
	at firrtl.options.Translator.transform(Phase.scala:248)
	at firrtl.options.Translator.transform$(Phase.scala:248)
	at firrtl.stage.phases.Compiler.transform(Compiler.scala:53)
	at firrtl.stage.phases.CatchExceptions.transform(CatchExceptions.scala:23)
	... 35 more

Your environment

running rocket-chip (version 1.5) with below chisel version

• Chisel Verions: 3.5.4
• OS: Linux xyz 3.10.0-1160.62.1.el7.x86_64 #1_ SMP Wed Mar 23 09:04:02 UTC 2022 x86_64 x86_64 x86_64 GNU/Linux
• Verilator version: 4.028.

External Information