Internal error when loading masked memory from file

[zyedidia]

Checklist

• Did you specify the current behavior?
• Did you specify the expected behavior?
• Did you provide a code example showing the problem?
• Did you describe your environment?
• Did you specify relevant external information?

What is the current behavior?

I am trying to make a memory that supports masked writes, and initialize it from a hex file for simulation. Following documentation online I arrived at:

package sys

import chisel3._
import chisel3.util._
import chisel3.util.experimental.loadMemoryFromFileInline

class RamIO(addrw: Int, dataw: Int) extends Bundle {
  val req = Output(Bool())
  val rvalid = Input(Bool())
  val we = Output(Bool())
  val be = Output(UInt((dataw / 8).W))
  val addr = Output(UInt(addrw.W))
  val wdata = Output(UInt(dataw.W))
  val rdata = Input(UInt(dataw.W))
}

class Ram(size: Int, addrw: Int, dataw: Int, memfile: String = "") extends Module {
  val io = IO(Flipped(new RamIO(addrw, dataw)))

  val MemType = Vec(dataw / 8, UInt(8.W))

  val mem = SyncReadMem(size, MemType)
  if (memfile.trim().nonEmpty) {
    loadMemoryFromFileInline(mem, memfile)
  }

  val rvalid = RegNext(io.req)
  io.rvalid := rvalid

  val addr = io.addr >> 2.U
  io.rdata := mem.read(addr, io.req).asTypeOf(UInt(dataw.W))

  when (io.req && io.we) {
    mem.write(addr, io.wdata.asTypeOf(MemType), io.be.asBools)
  }
}

object Ram extends App {
  (new chisel3.stage.ChiselStage).emitVerilog(new Ram(1024, 32, 32, "mem/test.hex"), Array("--target-dir", "generated"))
}

where mem/test.hex is

00500113
00c00193
ff718393
0023e233
0041f2b3
004282b3
02728863
0041a233
00020463
00000293
0023a233
005203b3
402383b3
0471aa23
06002103
005104b3
008001ef
00100113
00910133
0221a023
00210063

When I attempt to run this (generate Verilog) or run a test simulation it produces an internal error:

Full error message below:

[error] firrtl.FirrtlInternalException: Internal Error! Please file an issue at https://github.com/ucb-bar/firrtl/issues
[error]         at firrtl.Utils$.error(Utils.scala:471)
[error]         at firrtl.Utils$.throwInternalError(Utils.scala:175)
[error]         at firrtl.stage.phases.CatchExceptions.transform(CatchExceptions.scala:31)
[error]         at firrtl.stage.phases.CatchExceptions.transform(CatchExceptions.scala:10)
[error]         at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
[error]         at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
[error]         at firrtl.options.Translator.transform(Phase.scala:248)
[error]         at firrtl.options.Translator.transform$(Phase.scala:248)
[error]         at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
[error]         at firrtl.options.DependencyManager.$anonfun$transform$5(DependencyManager.scala:280)
[error]         at firrtl.Utils$.time(Utils.scala:181)
[error]         at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:280)
[error]         at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)
[error]         at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)
[error]         at scala.collection.immutable.List.foldLeft(List.scala:91)
[error]         at firrtl.options.DependencyManager.transform(DependencyManager.scala:269)
[error]         at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255)
[error]         at firrtl.options.PhaseManager.transform(DependencyManager.scala:443)
[error]         at firrtl.stage.FirrtlStage.run(FirrtlStage.scala:38)
[error]         at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
[error]         at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
[error]         at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
[error]         at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
[error]         at firrtl.options.Translator.transform(Phase.scala:248)
[error]         at firrtl.options.Translator.transform$(Phase.scala:248)
[error]         at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
[error]         at firrtl.options.Stage.$anonfun$transform$5(Stage.scala:47)
[error]         at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)
[error]         at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)
[error]         at scala.collection.immutable.List.foldLeft(List.scala:91)
[error]         at firrtl.options.Stage.$anonfun$transform$3(Stage.scala:47)
[error]         at logger.Logger$.$anonfun$makeScope$2(Logger.scala:137)
[error]         at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)
[error]         at logger.Logger$.makeScope(Logger.scala:135)
[error]         at firrtl.options.Stage.transform(Stage.scala:47)
[error]         at chisel3.stage.phases.MaybeFirrtlStage.$anonfun$transform$2(MaybeFirrtlStage.scala:22)
[error]         at scala.Option.getOrElse(Option.scala:189)
[error]         at chisel3.stage.phases.MaybeFirrtlStage.transform(MaybeFirrtlStage.scala:22)
[error]         at chisel3.stage.phases.MaybeFirrtlStage.transform(MaybeFirrtlStage.scala:13)
[error]         at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
[error]         at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
[error]         at firrtl.options.Translator.transform(Phase.scala:248)
[error]         at firrtl.options.Translator.transform$(Phase.scala:248)
[error]         at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
[error]         at firrtl.options.DependencyManager.$anonfun$transform$5(DependencyManager.scala:280)
[error]         at firrtl.Utils$.time(Utils.scala:181)
[error]         at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:280)
[error]         at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)
[error]         at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)
[error]         at scala.collection.immutable.List.foldLeft(List.scala:91)
[error]         at firrtl.options.DependencyManager.transform(DependencyManager.scala:269)
[error]         at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255)
[error]         at firrtl.options.PhaseManager.transform(DependencyManager.scala:443)
[error]         at chisel3.stage.ChiselStage.run(ChiselStage.scala:45)
[error]         at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
[error]         at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
[error]         at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
[error]         at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
[error]         at firrtl.options.Translator.transform(Phase.scala:248)
[error]         at firrtl.options.Translator.transform$(Phase.scala:248)
[error]         at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
[error]         at firrtl.options.Stage.$anonfun$transform$5(Stage.scala:47)
[error]         at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)
[error]         at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)
[error]         at scala.collection.immutable.List.foldLeft(List.scala:91)
[error]         at firrtl.options.Stage.$anonfun$transform$3(Stage.scala:47)
[error]         at logger.Logger$.$anonfun$makeScope$2(Logger.scala:137)
[error]         at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)
[error]         at logger.Logger$.makeScope(Logger.scala:135)
[error]         at firrtl.options.Stage.transform(Stage.scala:47)
[error]         at firrtl.options.Stage.execute(Stage.scala:58)
[error]         at chisel3.stage.ChiselStage.emitVerilog(ChiselStage.scala:101)
[error]         at sys.Ram$.delayedEndpoint$sys$Ram$1(Ram.scala:39)
[error]         at sys.Ram$delayedInit$body.apply(Ram.scala:38)
[error]         at scala.Function0.apply$mcV$sp(Function0.scala:39)
[error]         at scala.Function0.apply$mcV$sp$(Function0.scala:39)
[error]         at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:17)
[error]         at scala.App.$anonfun$main$1$adapted(App.scala:80)
[error]         at scala.collection.immutable.List.foreach(List.scala:431)
[error]         at scala.App.main(App.scala:80)
[error]         at scala.App.main$(App.scala:78)
[error]         at sys.Ram$.main(Ram.scala:38)
[error]         at sys.Ram.main(Ram.scala)
[error]         at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
[error]         at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)
[error]         at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
[error]         at java.base/java.lang.reflect.Method.invoke(Method.java:566)
[error] Caused by: java.lang.RuntimeException: [module Ram] Cannot initialize memory mem of non ground type UInt<8>[4]
[error]         at firrtl.passes.LowerTypes$.onStatement(LowerTypes.scala:179)
[error]         at firrtl.passes.LowerTypes$.$anonfun$onStatement$11(LowerTypes.scala:202)
[error]         at firrtl.ir.Block.mapStmt(IR.scala:653)
[error]         at firrtl.passes.LowerTypes$.onStatement(LowerTypes.scala:202)
[error]         at firrtl.passes.LowerTypes$.$anonfun$onModule$1(LowerTypes.scala:116)
[error]         at firrtl.ir.Module.mapStmt(IR.scala:1198)
[error]         at firrtl.passes.LowerTypes$.onModule(LowerTypes.scala:116)
[error]         at firrtl.passes.LowerTypes$.$anonfun$execute$4(LowerTypes.scala:86)
[error]         at scala.collection.TraversableLike.$anonfun$map$1(TraversableLike.scala:286)
[error]         at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:62)
[error]         at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:55)
[error]         at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:49)
[error]         at scala.collection.TraversableLike.map(TraversableLike.scala:286)
[error]         at scala.collection.TraversableLike.map$(TraversableLike.scala:279)
[error]         at scala.collection.AbstractTraversable.map(Traversable.scala:108)
[error]         at firrtl.passes.LowerTypes$.execute(LowerTypes.scala:86)
[error]         at firrtl.Transform.transform(Compiler.scala:280)
[error]         at firrtl.Transform.transform$(Compiler.scala:280)
[error]         at firrtl.passes.LowerTypes$.transform(LowerTypes.scala:41)
[error]         at firrtl.stage.transforms.ExpandPrepares.execute(ExpandPrepares.scala:19)
[error]         at firrtl.Transform.transform(Compiler.scala:280)
[error]         at firrtl.Transform.transform$(Compiler.scala:280)
[error]         at firrtl.stage.transforms.ExpandPrepares.transform(ExpandPrepares.scala:7)
[error]         at firrtl.stage.transforms.CatchCustomTransformExceptions.execute(CatchCustomTransformExceptions.scala:10)
[error]         at firrtl.Transform.transform(Compiler.scala:280)
[error]         at firrtl.Transform.transform$(Compiler.scala:280)
[error]         at firrtl.stage.transforms.CatchCustomTransformExceptions.transform(CatchCustomTransformExceptions.scala:7)
[error]         at firrtl.stage.transforms.UpdateAnnotations.internalTransform(UpdateAnnotations.scala:22)
[error]         at firrtl.stage.transforms.UpdateAnnotations.internalTransform(UpdateAnnotations.scala:8)
[error]         at firrtl.options.Translator.transform(Phase.scala:248)
[error]         at firrtl.options.Translator.transform$(Phase.scala:248)
[error]         at firrtl.stage.transforms.UpdateAnnotations.transform(UpdateAnnotations.scala:8)
[error]         at firrtl.options.DependencyManager.$anonfun$transform$5(DependencyManager.scala:280)
[error]         at firrtl.Utils$.time(Utils.scala:181)
[error]         at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:280)
[error]         at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)
[error]         at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)
[error]         at scala.collection.immutable.List.foldLeft(List.scala:91)
[error]         at firrtl.options.DependencyManager.transform(DependencyManager.scala:269)
[error]         at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255)
[error]         at firrtl.stage.TransformManager.transform(TransformManager.scala:14)
[error]         at firrtl.stage.phases.Compiler.$anonfun$internalTransform$6(Compiler.scala:138)
[error]         at firrtl.Utils$.time(Utils.scala:181)
[error]         at firrtl.stage.phases.Compiler.f$1(Compiler.scala:138)
[error]         at firrtl.stage.phases.Compiler.$anonfun$internalTransform$8(Compiler.scala:143)
[error]         at scala.collection.TraversableLike.$anonfun$map$1(TraversableLike.scala:286)
[error]         at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:62)
[error]         at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:55)
[error]         at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:49)
[error]         at scala.collection.TraversableLike.map(TraversableLike.scala:286)
[error]         at scala.collection.TraversableLike.map$(TraversableLike.scala:279)
[error]         at scala.collection.AbstractTraversable.map(Traversable.scala:108)
[error]         at firrtl.stage.phases.Compiler.internalTransform(Compiler.scala:143)
[error]         at firrtl.stage.phases.Compiler.internalTransform(Compiler.scala:53)
[error]         at firrtl.options.Translator.transform(Phase.scala:248)
[error]         at firrtl.options.Translator.transform$(Phase.scala:248)
[error]         at firrtl.stage.phases.Compiler.transform(Compiler.scala:53)
[error]         at firrtl.stage.phases.CatchExceptions.transform(CatchExceptions.scala:23)
[error]         at firrtl.stage.phases.CatchExceptions.transform(CatchExceptions.scala:10)
[error]         at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
[error]         at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
[error]         at firrtl.options.Translator.transform(Phase.scala:248)
[error]         at firrtl.options.Translator.transform$(Phase.scala:248)
[error]         at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
[error]         at firrtl.options.DependencyManager.$anonfun$transform$5(DependencyManager.scala:280)
[error]         at firrtl.Utils$.time(Utils.scala:181)
[error]         at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:280)
[error]         at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)
[error]         at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)
[error]         at scala.collection.immutable.List.foldLeft(List.scala:91)
[error]         at firrtl.options.DependencyManager.transform(DependencyManager.scala:269)
[error]         at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255)
[error]         at firrtl.options.PhaseManager.transform(DependencyManager.scala:443)
[error]         at firrtl.stage.FirrtlStage.run(FirrtlStage.scala:38)
[error]         at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
[error]         at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
[error]         at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
[error]         at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
[error]         at firrtl.options.Translator.transform(Phase.scala:248)
[error]         at firrtl.options.Translator.transform$(Phase.scala:248)
[error]         at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
[error]         at firrtl.options.Stage.$anonfun$transform$5(Stage.scala:47)
[error]         at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)
[error]         at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)
[error]         at scala.collection.immutable.List.foldLeft(List.scala:91)
[error]         at firrtl.options.Stage.$anonfun$transform$3(Stage.scala:47)
[error]         at logger.Logger$.$anonfun$makeScope$2(Logger.scala:137)
[error]         at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)
[error]         at logger.Logger$.makeScope(Logger.scala:135)
[error]         at firrtl.options.Stage.transform(Stage.scala:47)
[error]         at chisel3.stage.phases.MaybeFirrtlStage.$anonfun$transform$2(MaybeFirrtlStage.scala:22)
[error]         at scala.Option.getOrElse(Option.scala:189)
[error]         at chisel3.stage.phases.MaybeFirrtlStage.transform(MaybeFirrtlStage.scala:22)
[error]         at chisel3.stage.phases.MaybeFirrtlStage.transform(MaybeFirrtlStage.scala:13)
[error]         at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
[error]         at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
[error]         at firrtl.options.Translator.transform(Phase.scala:248)
[error]         at firrtl.options.Translator.transform$(Phase.scala:248)
[error]         at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
[error]         at firrtl.options.DependencyManager.$anonfun$transform$5(DependencyManager.scala:280)
[error]         at firrtl.Utils$.time(Utils.scala:181)
[error]         at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:280)
[error]         at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)
[error]         at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)
[error]         at scala.collection.immutable.List.foldLeft(List.scala:91)
[error]         at firrtl.options.DependencyManager.transform(DependencyManager.scala:269)
[error]         at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255)
[error]         at firrtl.options.PhaseManager.transform(DependencyManager.scala:443)
[error]         at chisel3.stage.ChiselStage.run(ChiselStage.scala:45)
[error]         at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
[error]         at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
[error]         at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
[error]         at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
[error]         at firrtl.options.Translator.transform(Phase.scala:248)
[error]         at firrtl.options.Translator.transform$(Phase.scala:248)
[error]         at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
[error]         at firrtl.options.Stage.$anonfun$transform$5(Stage.scala:47)
[error]         at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)
[error]         at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)
[error]         at scala.collection.immutable.List.foldLeft(List.scala:91)
[error]         at firrtl.options.Stage.$anonfun$transform$3(Stage.scala:47)
[error]         at logger.Logger$.$anonfun$makeScope$2(Logger.scala:137)
[error]         at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)
[error]         at logger.Logger$.makeScope(Logger.scala:135)
[error]         at firrtl.options.Stage.transform(Stage.scala:47)
[error]         at firrtl.options.Stage.execute(Stage.scala:58)
[error]         at chisel3.stage.ChiselStage.emitVerilog(ChiselStage.scala:101)
[error]         at sys.Ram$.delayedEndpoint$sys$Ram$1(Ram.scala:39)
[error]         at sys.Ram$delayedInit$body.apply(Ram.scala:38)
[error]         at scala.Function0.apply$mcV$sp(Function0.scala:39)
[error]         at scala.Function0.apply$mcV$sp$(Function0.scala:39)
[error]         at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:17)
[error]         at scala.App.$anonfun$main$1$adapted(App.scala:80)
[error]         at scala.collection.immutable.List.foreach(List.scala:431)
[error]         at scala.App.main(App.scala:80)
[error]         at scala.App.main$(App.scala:78)
[error]         at sys.Ram$.main(Ram.scala:38)
[error]         at sys.Ram.main(Ram.scala)
[error]         at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
[error]         at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)
[error]         at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
[error]         at java.base/java.lang.reflect.Method.invoke(Method.java:566)
[error] stack trace is suppressed; run last Compile / run for the full output
[error] Total time: 1 s, completed Mar 12, 2022 4:22:34 PM
[error] (Compile / run) firrtl.FirrtlInternalException: Internal Error! Please file an issue at https://github.com/ucb-bar/firrtl/issues

I think the error is caused by the memory masking, but I am not sure how to fix it (different hex file format? different Chisel implementation?). I couldn't find any details in the documentation.

What is the expected behavior?

I would expect it to generate Verilog with a readmemh statement to load the memory from a file. If there is a problem with my file format, I would expect it to give an error message about that.

Steps to Reproduce

See details above.

Your environment

• Chisel Version: 3.5.1

• OS: Linux mint 5.4.0-65-generic Ubuntu x86_64 GNU/Linux

• Verilator version: Verilator 4.028 2020-02-06 rev v4.026-92-g890cecc1

External Information

• Documentation for loading memory files: https://www.chisel-lang.org/chisel3/docs/appendix/experimental-features#loading-memories
• Documentation for masked memories: https://www.chisel-lang.org/chisel3/docs/explanations/memories.html#masks

[zyedidia]

I've determined that the "correct" way to do this is to avoid using a Vec memory and instead do the masking manually:

class Ram(size: Int, addrw: Int, dataw: Int, memfile: String = "") extends Module {
  val io = IO(Flipped(new RamIO(addrw, dataw)))

  val mem = SyncReadMem(size, UInt(dataw.W))
  if (memfile.trim().nonEmpty) {
    loadMemoryFromFileInline(mem, memfile)
  }

  val rvalid = RegNext(io.req)
  io.rvalid := rvalid

  val addr = io.addr / (dataw / 8).U
  io.rdata := mem.read(addr, io.req)

  val write = (0 until (dataw / 8)).foldLeft(0.U(dataw.W)) { (write, i) => 
    write |
      (Mux(
        io.req && io.be(i),
        io.wdata,
        mem(addr)
      )(8 * (i + 1) - 1, 8 * i) << (8 * i).U).asUInt
  }
  when (io.req && io.we) {
    mem.write(addr, write)
  }
}

Leaving this open since the original behavior is still a bug. I also noticed that this issue is related to #1289.

Note: this doesn't actually work the way you want, so you have to use an external verilog ram.