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Fix memory annotation deduplication (#2286)
* Add transform to deduplicate memory annotations * Add annotation deduplication to Dedup stage * ResolveAnnotationPaths and EliminateTargetPaths now invalidate the dedup annotations transform * Verilog emitter now throws exception when memory annotations fail to dedup Co-authored-by: Jack Koenig <koenig@sifive.com>
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101 changes: 101 additions & 0 deletions
101
src/main/scala/firrtl/transforms/DedupAnnotations.scala
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// SPDX-License-Identifier: Apache-2.0 | ||
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package firrtl | ||
package transforms | ||
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import firrtl.ir._ | ||
import firrtl.Mappers._ | ||
import firrtl.options.Dependency | ||
import firrtl.Utils.BoolType | ||
import firrtl.annotations.Annotation | ||
import scala.collection.mutable.Buffer | ||
import firrtl.annotations.MemoryFileInlineAnnotation | ||
import firrtl.passes.PassException | ||
import firrtl.annotations.ReferenceTarget | ||
import firrtl.annotations._ | ||
import firrtl.analyses.InstanceKeyGraph | ||
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import scala.collection.mutable.ArrayBuffer | ||
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object DedupAnnotationsTransform { | ||
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final class DifferingModuleAnnotationsException private (msg: String) extends PassException(msg) | ||
object DifferingModuleAnnotationsException { | ||
def apply(left: ReferenceTarget, right: ReferenceTarget): DifferingModuleAnnotationsException = { | ||
val msg = s"${left.serialize} and ${right.serialize} have differing module binaries" | ||
new DifferingModuleAnnotationsException(msg) | ||
} | ||
} | ||
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private case class DedupableRepr( | ||
dedupKey: Any, | ||
deduped: Annotation, | ||
original: Annotation, | ||
absoluteTarget: ReferenceTarget) | ||
private object DedupableRepr { | ||
def apply(annotation: Annotation): Option[DedupableRepr] = annotation.dedup match { | ||
case Some((dedupKey, dedupedAnno, absoluteTarget)) => | ||
Some(new DedupableRepr(dedupKey, dedupedAnno, annotation, absoluteTarget)) | ||
case _ => None | ||
} | ||
} | ||
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private type InstancePath = Seq[(TargetToken.Instance, TargetToken.OfModule)] | ||
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private def checkInstanceGraph( | ||
module: String, | ||
graph: InstanceKeyGraph, | ||
absolutePaths: Seq[InstancePath] | ||
): Boolean = graph.findInstancesInHierarchy(module).size == absolutePaths.size | ||
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def dedupAnnotations(annotations: Seq[Annotation], graph: InstanceKeyGraph): Seq[Annotation] = { | ||
val canDedup = ArrayBuffer.empty[DedupableRepr] | ||
val outAnnos = ArrayBuffer.empty[Annotation] | ||
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// Extract the annotations which can be deduplicated | ||
annotations.foreach { anno => | ||
DedupableRepr(anno) match { | ||
case Some(repr) => canDedup += repr | ||
case None => outAnnos += anno | ||
} | ||
} | ||
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// Partition the dedupable annotations into groups that *should* deduplicate into the same annotation | ||
val shouldDedup: Map[Any, ArrayBuffer[DedupableRepr]] = canDedup.groupBy(_.dedupKey) | ||
shouldDedup.foreach { | ||
case ((target: ReferenceTarget, _), dedupableAnnos) => | ||
val originalAnnos = dedupableAnnos.map(_.original) | ||
val uniqueDedupedAnnos = dedupableAnnos.map(_.deduped).distinct | ||
// TODO: Extend this to support multi-target annotations | ||
val instancePaths = dedupableAnnos.map(_.absoluteTarget.path).toSeq | ||
// The annotation deduplication is only legal if it applies to *all* instances of a | ||
// deduplicated module -- requires an instance graph check | ||
if (uniqueDedupedAnnos.size == 1 && checkInstanceGraph(target.encapsulatingModule, graph, instancePaths)) | ||
outAnnos += uniqueDedupedAnnos.head | ||
else | ||
outAnnos ++= originalAnnos | ||
} | ||
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outAnnos.toSeq | ||
} | ||
} | ||
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/** Deduplicates memory annotations | ||
*/ | ||
class DedupAnnotationsTransform extends Transform with DependencyAPIMigration { | ||
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override def prerequisites = Nil | ||
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override def optionalPrerequisites = Nil | ||
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override def optionalPrerequisiteOf = Nil | ||
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override def invalidates(a: Transform) = false | ||
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def execute(state: CircuitState): CircuitState = CircuitState( | ||
state.circuit, | ||
state.form, | ||
DedupAnnotationsTransform.dedupAnnotations(state.annotations.underlying, InstanceKeyGraph(state.circuit)), | ||
state.renames | ||
) | ||
} |
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