Switch from veneers to private macro interfaces

core/src/main/scala-2/chisel3/Aggregate.scala → core/src/main/scala-2/chisel3/AggregateIntf.scala

@@ -7,43 +7,7 @@ import chisel3.experimental.SourceInfo
 import chisel3.internal.HasId
 import chisel3.internal.sourceinfo.{SourceInfoTransform, VecTransform}
 
-/** An abstract class for data types that solely consist of (are an aggregate
-  * of) other Data objects.
-  */
-sealed trait Aggregate extends AggregateImpl
-
-/** A vector (array) of [[Data]] elements. Provides hardware versions of various
-  * collection transformation functions found in software array implementations.
-  *
-  * Careful consideration should be given over the use of [[Vec]] vs
-  * [[scala.collection.immutable.Seq Seq]] or some other Scala collection. In general [[Vec]] only
-  * needs to be used when there is a need to express the hardware collection in a [[Reg]] or IO
-  * [[Bundle]] or when access to elements of the array is indexed via a hardware signal.
-  *
-  * Example of indexing into a [[Vec]] using a hardware address and where the [[Vec]] is defined in
-  * an IO [[Bundle]]
-  *
-  *  {{{
-  *    val io = IO(new Bundle {
-  *      val in = Input(Vec(20, UInt(16.W)))
-  *      val addr = Input(UInt(5.W))
-  *      val out = Output(UInt(16.W))
-  *    })
-  *    io.out := io.in(io.addr)
-  *  }}}
-  *
-  * @tparam T type of elements
-  *
-  * @note
-  *  - when multiple conflicting assignments are performed on a Vec element, the last one takes effect (unlike Mem, where the result is undefined)
-  *  - Vecs, unlike classes in Scala's collection library, are propagated intact to FIRRTL as a vector type, which may make debugging easier
-  */
-sealed class Vec[T <: Data] private[chisel3] (gen: => T, length: Int)
-    extends VecImpl[T](gen, length)
-    with VecLike[T]
-    with Aggregate {
-
-  override def toString: String = super[VecImpl].toString
+private[chisel3] trait VecIntf[T <: Data] { self: Vec[T] =>
 
   override def do_apply(p: UInt)(implicit sourceInfo: SourceInfo): T = _applyImpl(p)
 
@@ -74,9 +38,7 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, length: Int)
   ): T = _reduceTreeImpl(redOp, layerOp)
 }
 
-object Vec extends VecFactory
-
-object VecInit extends VecInitImpl with SourceInfoDoc {
+private[chisel3] trait VecInit$Intf extends SourceInfoDoc { self: VecInit.type =>
 
   /** Creates a new [[Vec]] composed of elements of the input Seq of [[Data]]
     * nodes.
@@ -231,10 +193,7 @@ object VecInit extends VecInitImpl with SourceInfoDoc {
   ): Vec[T] = _iterateImpl(start, len)(f)
 }
 
-/** A trait for [[Vec]]s containing common hardware generators for collection
-  * operations.
-  */
-trait VecLike[T <: Data] extends VecLikeImpl[T] with SourceInfoDoc {
+private[chisel3] trait VecLikeImpl[T <: Data] extends SourceInfoDoc { self: VecLike[T] =>
 
   /** Creates a dynamically indexed read or write accessor into the array.
     */
@@ -301,10 +260,3 @@ trait VecLike[T <: Data] extends VecLikeImpl[T] with SourceInfoDoc {
   /** @group SourceInfoTransformMacro */
   def do_onlyIndexWhere(p: T => Bool)(implicit sourceInfo: SourceInfo): UInt = _onlyIndexWhereImpl(p)
 }
-
-/** Base class for Aggregates based on key values pairs of String and Data
-  *
-  * Record should only be extended by libraries and fairly sophisticated generators.
-  * RTL writers should use [[Bundle]].  See [[Record#elements]] for an example.
-  */
-abstract class Record extends RecordImpl with Aggregate

core/src/main/scala-2/chisel3/Bits.scala → core/src/main/scala-2/chisel3/BitsIntf.scala

@@ -27,15 +27,7 @@ private[chisel3] sealed trait ToBoolable extends Element {
   def do_asBool(implicit sourceInfo: SourceInfo): Bool
 }
 
-/** A data type for values represented by a single bitvector. This provides basic bitwise operations.
-  *
-  * @groupdesc Bitwise Bitwise hardware operators
-  * @define coll [[Bits]]
-  * @define sumWidthInt    @note The width of the returned $coll is `width of this` + `that`.
-  * @define sumWidth       @note The width of the returned $coll is `width of this` + `width of that`.
-  * @define unchangedWidth @note The width of the returned $coll is unchanged, i.e., the `width of this`.
-  */
-sealed abstract class Bits(private[chisel3] val width: Width) extends BitsImpl with ToBoolable {
+private[chisel3] trait BitsIntf extends ToBoolable { self: Bits =>
 
   /** Tail operator
     *
@@ -282,17 +274,7 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends BitsImpl w
   def do_##(that: Bits)(implicit sourceInfo: SourceInfo): UInt = _impl_##(that)
 }
 
-object Bits extends UIntFactory
-
-/** A data type for unsigned integers, represented as a binary bitvector. Defines arithmetic operations between other
-  * integer types.
-  *
-  * @define coll [[UInt]]
-  * @define numType $coll
-  * @define expandingWidth @note The width of the returned $coll is `width of this` + `1`.
-  * @define constantWidth  @note The width of the returned $coll is unchanged, i.e., `width of this`.
-  */
-sealed class UInt private[chisel3] (width: Width) extends Bits(width) with UIntImpl {
+private[chisel3] trait UIntIntf { self: UInt =>
 
   // TODO: refactor to share documentation with Num or add independent scaladoc
   /** Unary negation (expanding width)
@@ -555,17 +537,7 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with UIntI
   override def do_asSInt(implicit sourceInfo: SourceInfo): SInt = _asSIntImpl
 }
 
-object UInt extends UIntFactory
-
-/** A data type for signed integers, represented as a binary bitvector. Defines arithmetic operations between other
-  * integer types.
-  *
-  * @define coll [[SInt]]
-  * @define numType $coll
-  * @define expandingWidth @note The width of the returned $coll is `width of this` + `1`.
-  * @define constantWidth  @note The width of the returned $coll is unchanged, i.e., `width of this`.
-  */
-sealed class SInt private[chisel3] (width: Width) extends Bits(width) with SIntImpl {
+private[chisel3] trait SIntIntf { self: SInt =>
 
   /** Unary negation (constant width)
     *
@@ -738,9 +710,7 @@ sealed class SInt private[chisel3] (width: Width) extends Bits(width) with SIntI
   override def do_asSInt(implicit sourceInfo: SourceInfo): SInt = _asSIntImpl
 }
 
-object SInt extends SIntFactory
-
-sealed trait Reset extends ResetImpl with ToBoolable {
+private[chisel3] trait ResetIntf extends ToBoolable { self: Reset =>
 
   /** Casts this $coll to an [[AsyncReset]] */
   final def asAsyncReset: AsyncReset = macro SourceInfoWhiteboxTransform.noArg
@@ -755,16 +725,7 @@ sealed trait Reset extends ResetImpl with ToBoolable {
   def do_asDisable(implicit sourceInfo: SourceInfo): Disable = _asDisableImpl
 }
 
-object Reset {
-  def apply(): Reset = new ResetType
-}
-
-/** "Abstract" Reset Type inferred in FIRRTL to either [[AsyncReset]] or [[Bool]]
-  *
-  * @note This shares a common interface with [[AsyncReset]] and [[Bool]] but is not their actual
-  * super type due to Bool inheriting from abstract class UInt
-  */
-final class ResetType(private[chisel3] val width: Width = Width(1)) extends Reset with ResetTypeImpl with ToBoolable {
+private[chisel3] trait ResetTypeIntf extends ToBoolable { self: ResetType =>
 
   /** @group SourceInfoTransformMacro */
   def do_asAsyncReset(implicit sourceInfo: SourceInfo): AsyncReset = _asAsyncResetImpl
@@ -776,17 +737,7 @@ final class ResetType(private[chisel3] val width: Width = Width(1)) extends Rese
   def do_toBool(implicit sourceInfo: SourceInfo): Bool = do_asBool
 }
 
-object AsyncReset {
-  def apply(): AsyncReset = new AsyncReset
-}
-
-/** Data type representing asynchronous reset signals
-  *
-  * These signals are similar to [[Clock]]s in that they must be glitch-free for proper circuit
-  * operation. [[Reg]]s defined with the implicit reset being an [[AsyncReset]] will be
-  * asychronously reset registers.
-  */
-sealed class AsyncReset(private[chisel3] val width: Width = Width(1)) extends AsyncResetImpl with Reset {
+private[chisel3] trait AsyncResetIntf { self: AsyncReset =>
   override def toString: String = stringAccessor("AsyncReset")
 
   /** @group SourceInfoTransformMacro */
@@ -799,14 +750,7 @@ sealed class AsyncReset(private[chisel3] val width: Width = Width(1)) extends As
   def do_toBool(implicit sourceInfo: SourceInfo): Bool = _asBoolImpl
 }
 
-// REVIEW TODO: Why does this extend UInt and not Bits? Does defining airth
-// operations on a Bool make sense?
-/** A data type for booleans, defined as a single bit indicating true or false.
-  *
-  * @define coll [[Bool]]
-  * @define numType $coll
-  */
-sealed class Bool() extends UInt(1.W) with BoolImpl with Reset {
+private[chisel3] trait BoolIntf extends ToBoolable { self: Bool =>
 
   // REVIEW TODO: Why does this need to exist and have different conventions
   // than Bits?
@@ -882,5 +826,3 @@ sealed class Bool() extends UInt(1.W) with BoolImpl with Reset {
   /** @group SourceInfoTransformMacro */
   def do_asAsyncReset(implicit sourceInfo: SourceInfo): AsyncReset = _asAsyncResetImpl
 }
-
-object Bool extends BoolFactory

core/src/main/scala-2/chisel3/ChiselEnum.scala → core/src/main/scala-2/chisel3/ChiselEnumIntf.scala

@@ -7,10 +7,7 @@ import scala.reflect.macros.blackbox.Context
 import chisel3.experimental.SourceInfo
 import chisel3.internal.sourceinfo.SourceInfoTransform
 
-abstract class EnumType(factory: ChiselEnum) extends EnumTypeImpl(factory) {
-
-  @deprecated("ChiselEnum annotations have been removed so selfAnnotating no longer does anything.", "Chisel 7.0")
-  def this(factory: ChiselEnum, selfAnnotating: Boolean) = this(factory)
+private[chisel3] trait EnumTypeIntf { self: EnumType =>
 
   final def ===(that: EnumType): Bool = macro SourceInfoTransform.thatArg
   final def =/=(that: EnumType): Bool = macro SourceInfoTransform.thatArg
@@ -27,7 +24,7 @@ abstract class EnumType(factory: ChiselEnum) extends EnumTypeImpl(factory) {
   def do_>=(that:  EnumType)(implicit sourceInfo: SourceInfo): Bool = _impl_>=(that)
 }
 
-abstract class ChiselEnum extends ChiselEnumImpl {
+private[chisel3] trait ChiselEnumIntf { self: ChiselEnum =>
   protected def Value:           Type = macro EnumMacros.ValImpl
   protected def Value(id: UInt): Type = macro EnumMacros.ValCustomImpl
 }

core/src/main/scala-2/chisel3/Clock.scala → core/src/main/scala-2/chisel3/ClockIntf.scala

@@ -6,12 +6,7 @@ import scala.language.experimental.macros
 import chisel3.experimental.SourceInfo
 import chisel3.internal.sourceinfo.SourceInfoTransform
 
-object Clock {
-  def apply(): Clock = new Clock
-}
-
-// TODO: Document this.
-sealed class Clock extends ClockImpl {
+private[chisel3] trait ClockIntf { self: Clock =>
 
   /** Returns the contents of the clock wire as a [[Bool]]. */
   final def asBool: Bool = macro SourceInfoTransform.noArg

core/src/main/scala-2/chisel3/Data.scala → core/src/main/scala-2/chisel3/DataIntf.scala

@@ -20,15 +20,7 @@ import chisel3.util.simpleClassName
 import scala.reflect.ClassTag
 import scala.util.Try
 
-/** This forms the root of the type system for wire data types. The data value
-  * must be representable as some number (need not be known at Chisel compile
-  * time) of bits, and must have methods to pack / unpack structured data to /
-  * from bits.
-  *
-  * @groupdesc Connect Utilities for connecting hardware components
-  * @define coll data
-  */
-abstract class Data extends DataImpl with SourceInfoDoc {
+private[chisel3] trait DataIntf extends SourceInfoDoc { self: Data =>
 
   /** Does a reinterpret cast of the bits in this node into the format that provides.
     * Returns a new Wire of that type. Does not modify existing nodes.
@@ -55,5 +47,3 @@ abstract class Data extends DataImpl with SourceInfoDoc {
   /** @group SourceInfoTransformMacro */
   def do_asUInt(implicit sourceInfo: SourceInfo): UInt = _asUIntImpl
 }
-
-object Data extends ObjectDataImpl

core/src/main/scala-2/chisel3/DisableIntf.scala

@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chisel3
+
+import chisel3.internal._
+import chisel3.experimental.{OpaqueType, SourceInfo}
+import chisel3.internal.sourceinfo.SourceInfoTransform
+
+import scala.language.experimental.macros
+import scala.collection.immutable.ListMap
+
+private[chisel3] trait DisableIntf { self: Disable =>
+
+  /** Logical not
+    *
+    * @return invert the logical value of this `Disable`
+    * @group Bitwise
+    */
+  final def unary_! : Disable = macro SourceInfoTransform.noArg
+
+  /** @group SourceInfoTransformMacro */
+  def do_unary_!(implicit sourceInfo: SourceInfo): Disable = _impl_unary_!
+}

core/src/main/scala-2/chisel3/FormalContractIntf.scala

@@ -6,7 +6,7 @@ import chisel3.experimental.SourceInfo
 import scala.language.experimental.macros
 import scala.reflect.macros.whitebox
 
-private[chisel3] trait FormalContract$Intf extends FormalContract$VirtualMethods {
+private[chisel3] trait FormalContract$Intf { self: FormalContract.type =>
 
   /** Create a `contract` block with one or more arguments and results. */
   def apply(head: Data, tail: Data*): (Any => Unit) => Any =

core/src/main/scala-2/chisel3/Mem.scala → core/src/main/scala-2/chisel3/MemIntf.scala

@@ -7,7 +7,7 @@ import scala.language.experimental.macros
 import chisel3.internal.sourceinfo.{MemTransform, SourceInfoTransform}
 import chisel3.experimental.SourceInfo
 
-object Mem extends ObjectMemImpl with SourceInfoDoc {
+private[chisel3] trait Mem$Intf extends SourceInfoDoc { self: Mem.type =>
 
   /** Creates a combinational/asynchronous-read, sequential/synchronous-write [[Mem]].
     *
@@ -34,9 +34,7 @@ object Mem extends ObjectMemImpl with SourceInfoDoc {
   def do_apply[T <: Data](size: Int, t: T)(implicit sourceInfo: SourceInfo): Mem[T] = _applyImpl(size, t)
 }
 
-sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt, protected val sourceInfo: SourceInfo)
-    extends MemBaseImpl[T]
-    with SourceInfoDoc {
+private[chisel3] trait MemBaseIntf[T <: Data] extends SourceInfoDoc { self: MemBase[T] =>
 
   // REVIEW TODO: make accessors (static/dynamic, read/write) combinations consistent.
 
@@ -165,20 +163,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt, protected
   ): Unit = _writeImpl(idx, data, mask, clock)
 }
 
-/** A combinational/asynchronous-read, sequential/synchronous-write memory.
-  *
-  * Writes take effect on the rising clock edge after the request. Reads are
-  * combinational (requests will return data on the same cycle).
-  * Read-after-write hazards are not an issue.
-  *
-  * @note when multiple conflicting writes are performed on a Mem element, the
-  * result is undefined (unlike Vec, where the last assignment wins)
-  */
-sealed class Mem[T <: Data] private[chisel3] (t: T, length: BigInt, sourceInfo: SourceInfo)
-    extends MemBase(t, length, sourceInfo)
-    with MemImpl[T]
-
-object SyncReadMem extends ObjectSyncReadMemImpl {
+private[chisel3] trait SyncReadMem$Intf extends SourceInfoDoc { self: SyncReadMem.type =>
 
   /** Creates a sequential/synchronous-read, sequential/synchronous-write [[SyncReadMem]].
     *
@@ -225,23 +210,7 @@ object SyncReadMem extends ObjectSyncReadMemImpl {
   ): SyncReadMem[T] = _applyImpl(size, t, ruw)
 }
 
-/** A sequential/synchronous-read, sequential/synchronous-write memory.
-  *
-  * Writes take effect on the rising clock edge after the request. Reads return
-  * data on the rising edge after the request. Read-after-write behavior (when
-  * a read and write to the same address are requested on the same cycle) is
-  * undefined.
-  *
-  * @note when multiple conflicting writes are performed on a Mem element, the
-  * result is undefined (unlike Vec, where the last assignment wins)
-  */
-sealed class SyncReadMem[T <: Data] private[chisel3] (
-  t:                  T,
-  n:                  BigInt,
-  val readUnderWrite: SyncReadMem.ReadUnderWrite,
-  sourceInfo:         SourceInfo
-) extends MemBase[T](t, n, sourceInfo)
-    with SyncReadMemImpl[T] {
+private[chisel3] trait SyncReadMemIntf[T <: Data] extends SourceInfoDoc { self: SyncReadMem[T] =>
 
   override def read(x: UInt): T = macro SourceInfoTransform.xArg