Merge pull request #3956 from alainmarcel/alainmarcel-patch-1

comp op return val
chipsalliance · Jan 13, 2024 · 4a12ee7 · 4a12ee7
2 parents 576839c + a0db16a
commit 4a12ee7
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Showing 9 changed files with 1,619 additions and 18 deletions.
diff --git a/tests/ArianeElab/ArianeElab.log b/tests/ArianeElab/ArianeElab.log
@@ -175808,9 +175808,9 @@ design: (work@top)
     |vpiParent:
     \_operation: , line:1974:9, endln:1974:52
     |vpiDecompile:1
-    |vpiSize:64
-    |UINT:1
-    |vpiConstType:9
+    |vpiSize:1
+    |BIN:1
+    |vpiConstType:3
 \_logic_typespec: (xlen_t), line:30:13, endln:30:29
   |vpiParent:
   \_ref_typespec: (work@top.i_ariane.ARIANE_MARCHID)

diff --git a/tests/BlackConst/BlackConst.log b/tests/BlackConst/BlackConst.log
@@ -3605,9 +3605,9 @@ design: (work@top)
       |vpiOperand:
       \_constant: , line:123:14, endln:123:27
         |vpiDecompile:0
-        |vpiSize:64
-        |UINT:0
-        |vpiConstType:9
+        |vpiSize:1
+        |BIN:0
+        |vpiConstType:3
       |vpiOperand:
       \_constant: , line:123:32, endln:123:33
         |vpiParent:

diff --git a/tests/ParamEquivOp/ParamEquivOp.log b/tests/ParamEquivOp/ParamEquivOp.log
diff --git a/tests/ParamEquivOp/ParamEquivOp.sl b/tests/ParamEquivOp/ParamEquivOp.sl
@@ -0,0 +1 @@
+-parse -d uhdm -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin
diff --git a/tests/ParamEquivOp/dut.sv b/tests/ParamEquivOp/dut.sv
@@ -0,0 +1,44 @@
+
+module GOOD();
+endmodule
+
+
+module top();
+
+parameter p_edma_irq_read_clear     = 1'b0;
+parameter p_edma_tx_pkt_buffer      = 1'b1;
+parameter p_edma_rx_pkt_buffer      = 1'b1;
+parameter p_edma_queues             = 32'd1;
+parameter p_edma_tsu                = 1'b1;
+parameter p_edma_axi                = 1'b1;
+parameter p_edma_has_pcs            = 1'b1;
+parameter p_edma_ext_fifo_interface = 1'b0;
+parameter p_has_dma                 = (p_edma_ext_fifo_interface == 1'b0);
+
+// Define interrupt bits which actually exists
+parameter p_int_exists  = {
+                            2'b11,                    // 31:30
+                            (p_edma_tsu == 1),        // 29
+                            2'b11,                    // 28:27
+                            (p_edma_tsu == 1),        // 26
+                            8'b11111111,              // 25:18
+                            (p_edma_has_pcs == 1),    // 17
+                            (p_edma_has_pcs == 1),    // 16
+                            4'b1111,                  // 15:12
+                            (p_has_dma == 1),         // 11
+                            1'b1,                     // 10
+                            (p_edma_has_pcs == 0),    // 9
+                            1'b0,                     // 8 Reserved
+                            1'b1,                     // 7
+                            (p_has_dma == 1),         // 6
+                            2'b11,                    // 5:4
+                            (p_has_dma == 1),         // 3
+                            (p_has_dma == 1),         // 2
+                            2'b11 // 1:0
+                          };
+
+if (p_int_exists == 32'b11111111111111111111110011111111) begin
+  GOOD good();
+end
+
+endmodule
diff --git a/tests/ParamOverload3/ParamOverload3.log b/tests/ParamOverload3/ParamOverload3.log
@@ -3409,9 +3409,9 @@ design: (work@top)
     |vpiParent:
     \_operation: , line:52:9, endln:52:52
     |vpiDecompile:1
-    |vpiSize:64
-    |UINT:1
-    |vpiConstType:9
+    |vpiSize:1
+    |BIN:1
+    |vpiConstType:3
 \_int_typespec: , line:44:15, endln:44:27
   |vpiParent:
   \_ref_typespec: (work@top.NUM_FORMATS)

diff --git a/third_party/UHDM b/third_party/UHDM
diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
@@ -65,21 +65,21 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess;
 -- Generating done
 -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess
 [  6%] Generating 10_lsu_bus_intf.sv
-[ 12%] Generating 11_ifu_bp_ctl.sv
-[ 18%] Generating 12_beh_lib.sv
+[ 12%] Generating 12_beh_lib.sv
+[ 18%] Generating 11_ifu_bp_ctl.sv
 [ 25%] Generating 13_ifu_mem_ctl.sv
 [ 31%] Generating 14_mem_lib.sv
+[ 37%] Generating 15_exu.sv
 [ 43%] Generating 16_dec_decode_ctl.sv
-[ 43%] Generating 15_exu.sv
 [ 50%] Generating 1_lsu_stbuf.sv
 [ 56%] Generating 2_ahb_to_axi4.sv
 [ 62%] Generating 3_rvjtag_tap.sv
 [ 68%] Generating 4_dec_tlu_ctl.sv
 [ 75%] Generating 5_lsu_bus_buffer.sv
 [ 81%] Generating 7_axi4_to_ahb.sv
-[ 87%] Generating 6_dbg.sv
+[ 87%] Generating 8_ifu_aln_ctl.sv
+[ 93%] Generating 6_dbg.sv
 [100%] Generating 9_tb_top.sv
-[100%] Generating 8_ifu_aln_ctl.sv
 [100%] Built target Parse
 Surelog parsing status: 0
 [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/uvm_pkg.sv".

diff --git a/third_party/tests/oh/BasicOh.log b/third_party/tests/oh/BasicOh.log
@@ -19845,9 +19845,9 @@ design: (work@oh_fifo_async)
             |vpiOperand:
             \_constant: , line:68:28, endln:68:34
               |vpiDecompile:1
-              |vpiSize:64
-              |UINT:1
-              |vpiConstType:9
+              |vpiSize:1
+              |BIN:1
+              |vpiConstType:3
             |vpiOperand:
             \_part_select: rd_reg (work@oh_fifo_async.oh_memory_dp.genblk1.rd_reg), line:68:38, endln:68:51
               |vpiParent: