Clear sram as early as possible

src/core/core_top.sv

@@ -287,7 +287,7 @@ wire    [31:0]  cmd_bridge_rd_data;
 
 // bridge host commands
 // synchronous to clk_74a
-wire            status_boot_done  = pll_core_locked_s; 
+wire            status_boot_done  = pll_core_locked_s & sram_wipe_done_s; 
 wire            status_setup_done = pll_core_locked_s; // rising edge triggers a target command
 wire            status_running    = reset_n; // we are running as soon as reset_n goes high
 
@@ -517,6 +517,8 @@ synch_3 #(.WIDTH(32)) s06 (cont3_key,       cont3_key_s,        clk_sys);
 synch_3 #(.WIDTH(32)) s07 (cont4_key,       cont4_key_s,        clk_sys);
 synch_3 #(.WIDTH(32)) s08 (boot_settings,   boot_settings_s,    clk_sys);
 synch_3 #(.WIDTH(32)) s09 (run_settings,    run_settings_s,     clk_sys);
+synch_3               s10 (sram_wipe_done,  sram_wipe_done_s,   clk_74a);
+
 
 logic sgb_en, rumble_en, originalcolors, ff_snd_en, ff_en, sgb_border_en, gba_en;
 logic [1:0] tint;
@@ -739,9 +741,13 @@ sync_fifo #(
   .write_en_s (                                 )
 );
 
+wire sram_wipe_done, sram_wipe_done_s;
+
 cart_top cart
 (
   .reset                      ( reset             ),
+  .sram_rst                   ( ~pll_core_locked  ),
+  .sram_wipe_done             ( sram_wipe_done    ),
 
   .clk_sys                    ( clk_sys           ),
   .ce_cpu                     ( ce_cpu            ),

src/gb/cart.v

@@ -1,5 +1,6 @@
 module cart_top (
 	input         reset,
+	input         sram_rst,
 
 	input         clk_sys,
 	input         ce_cpu,
@@ -78,7 +79,9 @@ module cart_top (
   output        sram_oe_n,
   output        sram_we_n,
   output        sram_ub_n,
-  output        sram_lb_n
+  output        sram_lb_n,
+
+  output        sram_wipe_done
 );
 ///////////////////////////////////////////////////
 
@@ -439,8 +442,9 @@ assign bk_q     = cram_q_o;
 sram u_cram
 (
   // Clock and Reset
-  .clk        ( clk_sys       ), //! Input Clock
-  .reset      ( cart_download ), //! Reset
+  .clk        		( clk_sys       		), //! Input Clock
+  .reset      		( sram_rst      		), //! Reset
+  .sram_wipe_done ( sram_wipe_done    ),
 
   // Single Port Internal Bus Interface
   .we         ( bk_en ? bk_wr     : cram_wr                   ), //! Write Enable

src/gb/sram_128k_x1_x16.sv

@@ -35,13 +35,16 @@ module sram
         // Clock and Reset
         input  wire        clk,       //! Input Clock
         input  wire        reset,     //! Reset
+        output wire        sram_wipe_done,
+
         // Single Port Internal Bus Interface
         input  wire        we,        //! Write Enable
         input  wire        ub,
         input  wire        lb,
         input  wire [16:0] addr,      //! Address In
         input  wire [15:0] d,         //! Data In
         output  reg [15:0] q,         //! Data Out
+
         // SRAM External Interface
         output  reg [16:0] sram_addr, //! Address Out
         inout   reg [15:0] sram_dq,   //! Data In/Out
@@ -52,7 +55,6 @@ module sram
     );
 
     typedef enum logic [1:0] {
-        IDLE,
         RESET_MEMORY,
         NORMAL_OPERATION
     } state_t;
@@ -78,6 +80,7 @@ module sram
     always_ff @(posedge clk) begin : sramFSM
         case (state)
             RESET_MEMORY: begin
+                sram_wipe_done    <= 0;
                 {sram_lb_n, sram_ub_n} <= 2'b00;     // Unmask Low/High Byte
                 sram_addr <= reset_counter;          // Set Address
                 sram_dq   <= 16'h0000;               // Write Zeros
@@ -91,6 +94,7 @@ module sram
                 end
             end
             NORMAL_OPERATION: begin
+                sram_wipe_done    <= 1;
                 sram_addr <= {17{1'bX}};             // Set Address as "Don't Care"
                 sram_dq   <= {16{1'bZ}};             // Set Data Bus as High Impedance (Tristate)
                 if(we) begin
@@ -100,7 +104,7 @@ module sram
                     sram_dq   <= d;                  // Write Data
                 end
                 else begin
-                    {sram_lb_n, sram_ub_n} <= 2'b00;     // Mask Low/High Byte 
+                    {sram_lb_n, sram_ub_n} <= 2'b00; // Mask Low/High Byte 
                     {sram_oe_n, sram_we_n} <= 2'b01; // Write Disabled/Output Enabled
                     sram_addr <= addr;               // Set Address
                     q         <= sram_dq;            // Read Data
@@ -109,7 +113,7 @@ module sram
             end
 
             default: begin
-                next_state <= IDLE;
+                next_state <= RESET_MEMORY;
             end
         endcase
     end