Erase SRAM on startup

src/ap_core.qsf

@@ -324,7 +324,6 @@ set_global_assignment -name GENERATE_RBF_FILE ON
 # Signal Tap Assignments
 # ======================
 set_global_assignment -name ENABLE_SIGNALTAP OFF
-set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
 
 # Power Estimation Assignments
 # ============================
@@ -811,11 +810,9 @@ set_global_assignment -name QIP_FILE apf/apf.qip
 set_global_assignment -name QIP_FILE apf/mf_ddio_bidir_12.qip
 set_global_assignment -name VERILOG_FILE core/core_bridge_cmd.v
 set_global_assignment -name SDC_FILE core/core_constraints.sdc
-set_global_assignment -name SIGNALTAP_FILE core/stp1.stp
 set_global_assignment -name QIP_FILE core/mf_pllbase.qip
 set_global_assignment -name SIP_FILE core/mf_pllbase.sip
 set_global_assignment -name SOURCE_FILE db/ap_core.cmp.rdb
-set_global_assignment -name SIGNALTAP_FILE stp1.stp
 set_global_assignment -name QIP_FILE gb/rtc_ram/rtc_ram.qip
 set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
 set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION NEVER

src/apf/build_id.mif

@@ -10,7 +10,7 @@ CONTENT
 BEGIN
 
    0E0 : 20240725;
-   0E1 : 00181442;
-   0E2 : 53904e6c;
+   0E1 : 00214947;
+   0E2 : 55079a6c;
 
 END;

src/gb/cart.v

@@ -434,13 +434,13 @@ wire [15:0] cram_q_o;
 
 assign cram_q_h = cram_q_o[15:8];
 assign cram_q_l = cram_q_o[7:0];
-assign bk_q = cram_q_o;
+assign bk_q     = cram_q_o;
 
 sram u_cram
 (
   // Clock and Reset
-  .clk        ( clk_sys                     ), //! Input Clock
-  .reset      ( cart_download               ), //! Reset
+  .clk        ( clk_sys       ), //! Input Clock
+  .reset      ( cart_download ), //! Reset
 
   // Single Port Internal Bus Interface
   .we         ( bk_en ? bk_wr     : cram_wr                   ), //! Write Enable
@@ -451,12 +451,12 @@ sram u_cram
   .q          ( cram_q_o ), //! Data Out
 
   // SRAM External Interface
-  .sram_addr  ( sram_addr                   ), //! Address Out
-  .sram_dq    ( sram_dq                     ), //! Data In/Out
-  .sram_oe_n  ( sram_oe_n                   ), //! Output Enable
-  .sram_we_n  ( sram_we_n                   ), //! Write Enable
-  .sram_ub_n  ( sram_ub_n                   ), //! Upper Byte Mask
-  .sram_lb_n  ( sram_lb_n                   )  //! Lower Byte Mask
+  .sram_addr  ( sram_addr ), //! Address Out
+  .sram_dq    ( sram_dq   ), //! Data In/Out
+  .sram_oe_n  ( sram_oe_n ), //! Output Enable
+  .sram_we_n  ( sram_we_n ), //! Write Enable
+  .sram_ub_n  ( sram_ub_n ), //! Upper Byte Mask
+  .sram_lb_n  ( sram_lb_n )  //! Lower Byte Mask
 );
 
 endmodule

src/gb/sram_128k_x1_x16.sv

@@ -51,28 +51,67 @@ module sram
         output  reg        sram_lb_n  //! Lower Byte Mask
     );
 
-    always @(posedge clk) begin : RW_SRAM
+    typedef enum logic [1:0] {
+        IDLE,
+        RESET_MEMORY,
+        NORMAL_OPERATION
+    } state_t;
+
+    state_t state, next_state;
+    reg [16:0] reset_counter;
+
+    // State machine transitions
+    always_ff @(posedge clk or posedge reset) begin
         if(reset) begin
-            {sram_lb_n, sram_ub_n} <= 2'b11;     // Mask Low/High Byte
-            sram_addr <= {17{1'bX}};             // Set Address as "Don't Care"
-            sram_dq   <= {16{1'bZ}};             // Set Data Bus as High Impedance (Tristate)
+            state <= RESET_MEMORY;
+            reset_counter <= 0;
         end
         else begin
-            sram_addr <= {17{1'bX}};             // Set Address as "Don't Care"
-            sram_dq   <= {16{1'bZ}};             // Set Data Bus as High Impedance (Tristate)
-            if(we) begin
-                {sram_oe_n, sram_we_n} <= 2'b10; // Output Disabled/Write Enabled
-                {sram_lb_n, sram_ub_n} <= {~lb, ~ub};
-                sram_addr <= addr;               // Set Address
-                sram_dq   <= d;                  // Write Data
-            end
-            else begin
-                {sram_oe_n, sram_we_n} <= 2'b01; // Write Disabled/Output Enabled
-                {sram_lb_n, sram_ub_n} <= 2'b00;     // Mask Low/High Byte 
-                sram_addr <= addr;               // Set Address
-                q         <= sram_dq;            // Read Data
+            state <= next_state;
+            if (state == RESET_MEMORY) begin
+                reset_counter <= reset_counter + 1;
             end
         end
     end
 
+    // State machine logic
+    always_ff @(posedge clk) begin : sramFSM
+        case (state)
+            RESET_MEMORY: begin
+                {sram_lb_n, sram_ub_n} <= 2'b00;     // Unmask Low/High Byte
+                sram_addr <= reset_counter;          // Set Address
+                sram_dq   <= 16'h0000;               // Write Zeros
+                {sram_oe_n, sram_we_n} <= 2'b10;     // Output Disabled/Write Enabled
+
+                if (reset_counter == 17'h1FFFF) begin
+                    next_state <= NORMAL_OPERATION;
+                end
+                else begin
+                    next_state <= RESET_MEMORY;
+                end
+            end
+            NORMAL_OPERATION: begin
+                sram_addr <= {17{1'bX}};             // Set Address as "Don't Care"
+                sram_dq   <= {16{1'bZ}};             // Set Data Bus as High Impedance (Tristate)
+                if(we) begin
+                    {sram_lb_n, sram_ub_n} <= {~lb, ~ub};
+                    {sram_oe_n, sram_we_n} <= 2'b10; // Output Disabled/Write Enabled
+                    sram_addr <= addr;               // Set Address
+                    sram_dq   <= d;                  // Write Data
+                end
+                else begin
+                    {sram_lb_n, sram_ub_n} <= 2'b00;     // Mask Low/High Byte 
+                    {sram_oe_n, sram_we_n} <= 2'b01; // Write Disabled/Output Enabled
+                    sram_addr <= addr;               // Set Address
+                    q         <= sram_dq;            // Read Data
+                end
+                next_state <= NORMAL_OPERATION;
+            end
+
+            default: begin
+                next_state <= IDLE;
+            end
+        endcase
+    end
+
 endmodule