Commits

Branch selector

 master

User selector

All users

Datepicker

All time

Commit History

Commits on Sep 27, 2022

• Skip PC increment after SYNC cycle if IRQ is active.

  brianhuffman

  committed
  211c12f

• Initial implementation of IRQ handling.

  brianhuffman

  committed
  548ac92

Commits on Sep 26, 2022

• Fix bug: JMP() shouldn't set I flag.

  brianhuffman

  committed
  aba1b3d

• Combine write.a and write.p signals into one signal write.push.

  brianhuffman

  committed
  f88a761

• Make BRK instruction set I flag.

  brianhuffman

  committed
  5a6fe4b

Commits on Sep 19, 2022

• Fix bug: Output RMW result computed in first cycle before C is updated.

  brianhuffman

  committed
  e37ddd2

Commits on Sep 14, 2022

• Fix bug: Set PC correctly after JSR cycle 6.

  brianhuffman

  committed
  d418dce

• Implement CPX/CPY instructions.

  brianhuffman

  committed
  c4c7a4d

• Fix startup state to load reset vector.

  brianhuffman

  committed
  9c33b9d

Commits on Sep 13, 2022

• Fix bug: Only use decimal carry for ADC, not SBC.

  Show description for a9ebf72
  brianhuffman

  committed
  a9ebf72

• Implement decimal mode behavior for ADC/SBC.

  brianhuffman

  committed
  bd9c7fe

Commits on Sep 12, 2022

• Fix bug: Add control signal to implement TXS instruction.

  brianhuffman

  committed
  a6b030b

Commits on Sep 11, 2022

• Fix bug: Use signal control.db.s to make TSX instruction work.

  brianhuffman

  committed
  6bf8c96

• Fix bug: Output address = PC in cycle 6 of JSR.

  brianhuffman

  committed
  b7063a1

• Fix bug: Make CLV instruction clear V instead of setting it.

  brianhuffman

  committed
  0b08c8b

Commits on Sep 10, 2022

• Fix bug: Increment ADL before last cycle of BRK.

  brianhuffman

  committed
  2774076

• Fix bug: Use correct address and PC in last cycle of RTS.

  brianhuffman

  committed
  94e3687

• Fix bug: Add transition from zeropage2 to modify1 for RMW instructions.

  brianhuffman

  committed
  ea62c99

Commits on Aug 28, 2022

• Split control signals for ADH and ADL.

  brianhuffman

  committed
  7a09f68

• Fix bug: For control.addr.inc, use base address from the right cycle.

  brianhuffman

  committed
  07a645f

Commits on Aug 27, 2022

• Implement JMP() instruction.

  brianhuffman

  committed
  a4d88ab

• Use indexing unit to do address increment for loading vectors.

  brianhuffman

  committed
  34cdf80

Commits on Aug 21, 2022

• Make CMP instructions set the C flag.

  brianhuffman

  committed
  d6033e2

• Fix ALU to output correct result for CMP.

  brianhuffman

  committed
  82f250f

• Fix CMP instructions to always set C flag in ALU.

  brianhuffman

  committed
  6a4d4a3

Commits on Aug 20, 2022

• Combine reg_fixpage with reg_index, and combine corresponding adders.

  brianhuffman

  committed
  5fee246

• Compute RMW operation during modify1 cycle instead of modify2.

  brianhuffman

  committed
  1b23fa2

• Merge incrementer/decrementers for X and Y into new counter unit.

  brianhuffman

  committed
  fa81df1

• Combine adders in RMW unit inc/dec.

  brianhuffman

  committed
  793cb15

• Combine separate accumulator and memory RMW units.

  brianhuffman

  committed
  6289ad5

Commits on Aug 19, 2022

• Merge adders for INX/DEX and INY/DEY.

  brianhuffman

  committed
  c56b97d

• Fix bug in opcode decoding of TAY.

  brianhuffman

  committed
  c54d0cf

• Fix bug: NZ flags updated by BCS/CLV instructions.

  brianhuffman

  committed
  f015257

Commits on Aug 18, 2022

• Refactor code for N/Z control signals.

  brianhuffman

  committed
  545558a

• Refactor control signals for updating A,X,Y,N,Z.

  brianhuffman

  committed
  3999e71

Pagination

PreviousNext