Fix ALU to output correct result for CMP.

brianhuffman · Aug 21, 2022 · 82f250f · 82f250f
1 parent 6a4d4a3
commit 82f250f
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/verilog/cpu6502.sv b/verilog/cpu6502.sv
@@ -846,7 +846,7 @@ module cpu6502_alu
             3'h3: result = add_result;  // ADC
             3'h4: result = 8'h0;        // STA
             3'h5: result = b_in;        // LDA
-            3'h6: result = a_in;        // CMP
+            3'h6: result = add_result;  // CMP
             3'h7: result = add_result;  // SBC
         endcase // case (op)
     end