Fix bug: Add transition from zeropage2 to modify1 for RMW instructions.

brianhuffman · Sep 10, 2022 · ea62c99 · ea62c99
1 parent 7a09f68
commit ea62c99
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/verilog/cpu6502.sv b/verilog/cpu6502.sv
@@ -409,7 +409,8 @@ module cpu6502
             control.adl.index = 1;
             control.index.inc = opcode_indirect_x;
             next_state.indirect = opcode_indirect_x; // xxx_000_x1 (01,03)
-            next_state.byte1 = ~opcode_indirect_x;    // xxx_101_xx (14,15,16,17)
+            next_state.modify1 = ~opcode_indirect_x & opcode_modify;
+            next_state.byte1 = ~opcode_indirect_x & ~opcode_modify;
         end
 
         if (reg_state.byte3)