Repository navigation
[W4] Via-in-pad process and paste need explicit order review #12
Description
Review finding W4, recorded 2026-10-14 for bonanzaDisplay v3. Original classification: Warning — assembly confirmation.
Location: U1 exposed pad; J1/J5 mounting tabs; R40 pad 2.
Current status: Local design review complete. No PCB change required for this finding when using JLCPCB's included six-layer epoxy-filled and copper-capped via process (POFV). The owner confirmed the six-layer product choice. JLCPCB's current via-covering guidance confirms free resin filling for six-layer and higher boards; its POFV announcement explicitly includes copper capping. Actual order selection and supplier stencil/CAM/assembly previews remain to be checked at release.
Original concern: Open vias in solder pads can wick solder out of the joint. Tenting alone would not resolve that concern. Filled and copper-capped vias provide the intended solderable surface.
Local review: Read the current canonical board through KiCad's native API and generated fresh bottom paste/mask plots. U1 pad 61 has five 0.30 mm vias and a 3 × 3 pattern of rounded 0.91 mm paste apertures: approximately 61% exposed-pad coverage and 0.22 mm webs. J1/J5 anchor paste openings are present. R40 pad 2 has a centered 0.30 mm via, with matching paste apertures on both resistor terminals. No obvious aperture defect was found at the tracked locations. This is a geometry review, not a solder-process qualification.
Process: Use epoxy-filled and copper-capped vias for all 0.25/0.30 mm through vias, including via-in-pad. Do not fill component insertion or mechanical holes. Do not replace the intended process with tenting-only treatment. The separate copper-fill option is not required by this design.
Completion criteria:
- Confirm the chosen six-layer product includes the required filled-and-capped via process.
- Review current local paste/mask geometry at U1, J1/J5 anchors, and R40.
- Document the fabrication requirement in README (committed in
57bda588457781f5eb5f50349efcc6c145367529). - Confirm filled-and-capped treatment in the actual order details.
- Review supplier stencil/CAM and assembly previews for these locations before release.
Evidence: JLCPCB via-covering guidance, free POFV process. Local review artifacts: review/w4-via-in-pad/ (ignored).
Activity
skot commentedon Oct 14, 2026
Add R40 pad 2 to the via-in-pad manufacturing/stencil review. The owner's reviewed BOOT routing adjustment puts the through via at (146.26, 61.93 mm), centered in that 0402 resistor pad. Included in local commit
72f574b31f454c2da597cdfbb2de53fac2dd011d(not pushed). DRC passes after zone refill. Confirm the actual filled/capped via process and the R40 paste/assembly preview along with the previously listed U1 and connector locations.Sync reviewed v3.1 PCB fixes and protect BOOT chip-select
skot commentedon Oct 14, 2026
Confirmed: the intended JLCPCB six-layer product includes epoxy-filled and copper-capped vias at no extra process charge. The via-in-pad layout can remain as designed; the separate copper-fill option is not necessary.
I checked the saved board and fresh B.Paste/B.Mask plots. U1's nine rounded paste windows give approximately 61% coverage with 0.22 mm webs; J1/J5 anchor paste is present; R40's two paste openings match. The tracked vias are 0.30 mm drill with 0.45/0.50 mm pads. The 19 vias adjusted for #11 are 0.25 mm drill / 0.45 mm pad and also fit the selected process.
Added the process requirement and release checks to README. No native PCB or schematic changes were made for #12. Documentation is uncommitted, so there is no new commit reference yet. Leaving this issue open only for actual order confirmation and supplier stencil/CAM/assembly preview checks, which cannot be signed off from local geometry alone.
skot commentedon Oct 15, 2026
The reviewed fabrication/process documentation is now included in local commit
57bda588457781f5eb5f50349efcc6c145367529(not pushed). Keeping this issue open for confirmation of filled-and-capped treatment in the actual order and review of supplier stencil/CAM and assembly previews.Apply reviewed fabrication rules and ERC model fixes