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[W3] Project rules do not enforce all relevant fabrication clearances #11
Description
Review finding W3, recorded 2026-10-14 for bonanzaDisplay v3. Original classification: Warning — DFM coverage.
Location: Project design settings
Current status: Manually reviewed and committed in 57bda588457781f5eb5f50349efcc6c145367529 (local, not pushed). DRC reports zero violations, zero unconnected items and zero schematic-parity findings. The selected via sizes meet the published no-small-via-surcharge condition for the intended six-layer process.
Original observation: Minimum copper-to-edge clearance is 0 mm, minimum silk clearance is 0 mm, and silk-over-copper checking is ignored. Minimum hole-to-copper clearance is 0.15 mm. There are no individually excluded ERC/DRC findings.
Why it matters: JLCPCB lists 0.2 mm routed copper-edge clearance and several hole-clearance requirements above the configured 0.15 mm. Therefore the clean project DRC is not a complete JLCPCB DFM sign-off. This identifies a rule-coverage gap, not a proven copper-edge violation.
Recommended action: Apply current JLCPCB limits appropriate to the chosen six-layer process and rerun DRC, including copper-edge, hole-to-copper and silkscreen checks. Review any intentional exceptions rather than globally suppressing them.
Completion criteria:
- Configure relevant JLCPCB copper-edge, hole and silkscreen rules for the ordered process.
- Rerun DRC and document any deliberate exceptions individually.
Evidence: JLCPCB fabrication capabilities
- Complete manual review and record the commit containing the rules and PCB corrections.
Activity
skot commentedon Oct 14, 2026
Implemented W3 in the main project, including PCB corrections. Uncommitted; ready for manual review.
bonanzaDisplay.kicad_dru.Validation after zone refill: 0 DRC violations, 0 unconnected items, 0 schematic-parity findings. All 69 footprint placements and pad geometry, all via positions, track endpoints, and net assignments were preserved. The schematic is unchanged. The saved board was also visually reviewed.
Local evidence is in
review/w3-dfm/(ignored review artifacts), includingafter-fix-drc.json,parity.json, andverification.json. Exact ordering options/stackup, via-in-pad handling (#12), and final manufacturing outputs remain separate checks. This is not a guarantee of the complete order price.Leaving this issue open for manual review and a commit reference.
skot commentedon Oct 15, 2026
Manual review approved by the owner. Committed in
57bda588457781f5eb5f50349efcc6c145367529(local, not pushed), including the fabrication rules, PCB clearance/silkscreen corrections and corresponding library updates. Final pre-commit DRC: 0 violations, 0 unconnected items, 0 schematic-parity findings. Closing this design-rule issue; actual order and supplier previews remain tracked separately in #12 and #17.Apply reviewed fabrication rules and ERC model fixes