feat(ssnpm): Add support for pointer masking - #354
Open
ninolomata wants to merge 6 commits into
Open
Conversation
Signed-off-by: Bruno Sa <bruno.vilaca.sa@gmail.com>
Add the senvcfg CSR accessor and clear senvcfg during vCPU reset so guest-visible environment configuration starts from a known state. Signed-off-by: Bruno Sa <bruno.vilaca.sa@gmail.com>
Add RISC-V cache maintenance support around the Zicbom cache-block management instructions and expose Zicboz/Zicbom guest configuration through henvcfg when the platform enables those extensions. Introduce cache block helpers, implement cache_flush_range() with cbo.flush and ordering fences, and extend the RISC-V build flags to include Zicbom support. Also add per-platform extension toggles so ports can explicitly advertise or disable Zicboz/Zicbom support. Signed-off-by: Bruno Sa <bruno.vilaca.sa@gmail.com>
Signed-off-by: Bruno Sa <bruno.vilaca.sa@gmail.com>
Signed-off-by: Bruno Sa <bruno.vilaca.sa@gmail.com>
ninolomata
requested review from
DavidMCerdeira,
danielRep,
josecm,
malejo97,
miguelafsilva5 and
sandro2pinto
as code owners
April 9, 2026 14:44
Signed-off-by: Bruno Sa <bruno.vilaca.sa@gmail.com>
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Summary
Add initial RISC-V
Ssnpmsupport for programming the guest-visible PMM mode.This change:
HSTATUS_HUPMMfield definitionshenvcfgduring hypervisor initwhen
CPU_EXT_SSNPMis enabledCPU_EXT_SSNPMCPU_EXT_SSNPM_PMM_MODEDependency
This PR depends on:
It is intended to be reviewed and merged on top of that series, since it builds
on the related RISC-V extension plumbing already introduced there.
Implementation
The patch:
HSTATUS_HUPMMfield definitions in the RISC-V CSR headervmm_arch_init()to configure PMM mode whenCPU_EXT_SSNPMis enabledSsnpmis enabled and which PMM modeBao should advertise
The following PMM modes are supported:
HENVCFG_PMM_DISABLEDHENVCFG_PMM_PMLEN_7HENVCFG_PMM_PMLEN_16On RV32, the build fails explicitly since
Ssnpmis not available there.Requirements to run
Running this support requires coordinated changes across Bao, the guest DT, and
QEMU.
Bao configuration
Enable cache-maintenance support in the Bao platform configuration for:
qemu-riscv32-virtqemu-riscv64-virtSet:
CPU_EXT_SSNPM = 1CPU_EXT_SSNPM_PMM_M = HENVCFG_PMM_PMLEN_7)Linux / Device Tree
It must also advertise the extensions in
riscv,isa.For RV32:
riscv,isa = "rv32imafdch_ssnpm_zicbom_zicboz_zicbop_zicntr_zicsr_zifencei_sstc";For RV64:
riscv,isa = "rv64imafdch_ssnpm_zicbom_zicboz_zicbop_zicntr_zicsr_zifencei_sstc";QEMU
A QEMU version with
ssnpmsupport is required, setssnpm=trueon the `cpu.https://github.com/ninolomata/qemu-bao/tree/riscv-rv32-henvcfg-stateen-fixesbao-demos(QEMU 10.0.2)