Add Zicboz and Zicbom cache maintenance support

[ninolomata]

Summary

Add RISC-V cache-maintenance support based on the Zicbom and Zicboz
extensions.

This change:

• adds cache-block operation helpers for cbo.clean, cbo.flush, and
  cbo.inval
• implements cache_flush_range() using Zicbom cache-block flushes when the
  extension is enabled
• adds the missing henvcfg field definitions needed to control cache-block
  management exposure
• programs henvcfg during hypervisor initialization to expose Zicboz and
  Zicbom only when the platform is configured to support them
• clears senvcfg during vCPU reset so guest-visible environment configuration
  starts from a known state
• enables Zicbom in the RISC-V build flags and advertises Zicboz/Zicbom
  in the qemu-riscv32-virt and qemu-riscv64-virt platform configurations

Implementation

The PR adds RISC-V cache-block helper wrappers in the cache header and uses
them in cache_flush_range() when CPU_EXT_ZICBOM is enabled. A weak fallback
implementation is preserved for platforms that do not provide cache maintenance.

On the virtualization side, henvcfg is reset during vmm_arch_init() and
then updated to enable:

• HENVCFG_CBZE for Zicboz
• HENVCFG_CBCFE | HENVCFG_CBIE_FLUSH for Zicbom

The configuration is verified through readback so unsupported WARL fields are
detected early.

The patch also adds the missing CSR definitions and resets senvcfg during
vCPU initialization to keep guest-visible state deterministic.

Requirements to run

Running this support requires coordinated changes across Bao, the guest DT, and
QEMU.

Bao configuration

Enable cache-maintenance support in the Bao platform configuration for:

• qemu-riscv32-virt
• qemu-riscv64-virt

Set:

• CPU_EXT_ZICBOM = 1
• CPU_EXT_ZICBOZ = 1

Linux / Device Tree

The guest DT must expose cache-block management support by adding:

• riscv,cbom-block-size = <64>;
• riscv,cboz-block-size = <64>;

It must also advertise the extensions in riscv,isa.

For RV32:

• riscv,isa = "rv32imafdch_zicbom_zicboz_zicntr_zicsr_zifencei_sstc";

For RV64:

• riscv,isa = "rv64imafdch_zicbom_zicboz_zicntr_zicsr_zifencei_sstc";

QEMU

A QEMU version with Zicbom/Zicboz support is required.

• RV32 QEMU:
  • use https://github.com/ninolomata/qemu-bao/tree/riscv-rv32-henvcfg-stateen-fixes
• RV64 QEMU:
  • use the same version currently used in bao-demos (QEMU 10.0.2)

[danielRep]

LGTM. Side question: Did you committed those qemu fixes upstream? Are they in already?

[josecm]

@ninolomata can you clean the history by incorporating the fixes into the original commit they were supposed to be part of?

[sandro2pinto]

All good to me.

[sandro2pinto]

All good to me.

[sandro2pinto]

All good to me.