Fix config space register region checks

alexforencich · Mar 8, 2022 · 067804e · 067804e
1 parent ed16549
commit 067804e
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/cocotbext/pcie/core/function.py b/cocotbext/pcie/core/function.py
@@ -249,10 +249,10 @@ async def read_config_register(self, reg):
             # Interrupt pin
             val |= (self.interrupt_pin & 0xff) << 8
             return val
-        elif 16 <= reg < 256:
+        elif 16 <= reg < 64:
             # PCIe capabilities
             return await self.read_capability_register(reg)
-        elif 256 <= reg < 4096:
+        elif 64 <= reg < 1024:
             # PCIe extended capabilities
             return await self.read_extended_capability_register(reg)
         else:
@@ -294,10 +294,10 @@ async def write_config_register(self, reg, data, mask):
             # Interrupt line
             if mask & 1:
                 self.interrupt_line = data & 0xff
-        elif 16 <= reg < 256:
+        elif 16 <= reg < 64:
             # PCIe capabilities
             await self.write_capability_register(reg, data, mask)
-        elif 256 <= reg < 4096:
+        elif 64 <= reg < 1024:
             # PCIe extended capabilities
             await self.write_extended_capability_register(reg, data, mask)