Update prefetchable base/limit register implementation

alexforencich · Dec 28, 2021 · ed16549 · ed16549
1 parent d72ba6b
commit ed16549
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/cocotbext/pcie/core/bridge.py b/cocotbext/pcie/core/bridge.py
@@ -161,6 +161,8 @@ async def read_config_register(self, reg):
             val = (self.prefetchable_mem_base & 0xfff00000) >> 16
             # Prefetchable memory limit
             val |= self.prefetchable_mem_limit & 0xfff00000
+            # supports 64 bit addresses
+            val |= 0x00010001
             return val
         elif reg == 10:
             # Prefetchable memory base (upper)