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Fix clock output enable bit. Fix register control input pull value. #32

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Merged
EdNutting merged 1 commit into from
Oct 29, 2018
Merged

Fix clock output enable bit. Fix register control input pull value. #32

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Empty file modified build.sh
100644 → 100755
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8 changes: 6 additions & 2 deletions src/com/modsim/modules/Clock.java
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Original file line number Diff line number Diff line change
Expand Up @@ -95,18 +95,22 @@ public void propagate() {

// Phase 1
BinData p1 = new BinData();
p1.setBit(0, (step == 1) ? 1 : 0);
p1.setBooleanBit(0, step == 1);
phase1.setEnabled(step == 1);

// Phase 2
BinData p2 = new BinData();
p2.setBit(0, (step == 3) ? 1 : 0);
p2.setBooleanBit(0, step == 3);
phase2.setEnabled(step == 3);

// Reset signal
p2.setBooleanBit(1, sendReset);
p1.setBooleanBit(1, sendReset);

// Enable signal
p2.setBooleanBit(2, true);
p1.setBooleanBit(2, true);

// Set the outputs
outputs.get(0).setVal(p1);
outputs.get(1).setVal(p2);
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2 changes: 1 addition & 1 deletion src/com/modsim/modules/Register.java
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Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,7 @@ public class Register extends BaseModule {
h = 50;

dataIn = addInput("Data in", 0, Port.DATA);
controlIn = addInput("Control in", 0, Port.CLOCK, new BinData(0, 1, 0, 0));
controlIn = addInput("Control in", 0, Port.CLOCK, new BinData(0, 1, 0, 1));

dataOut = addOutput("Data out", 0, Port.DATA);
controlOut = addOutput("Control out", 0, Port.CLOCK);
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