v1.0.3

- Add sim JtagTcp, UartEncoder, UartDecoder
- Improve memory usage, performance and scaling of design's errors reporting
- Fix verilator backend string imports
- Fix I2C controller interrupt x-prop

v1.0.2

- Add simExit()
- Add enum read/write support in sim
- Add sim seed
- Add sim wave depth
- Fix anonymous component naming
- Rework sim api includes
- Add sim ClockDomain stimulus generation utiles

v1.0.1

- Fix sim zerowidth io
- Fix sim clockdomain access

v1.0.0

- Add simulation capabilities via Verilator and an abstract API

v0.11.5

- Fix latch/unasigned signals for components inputs
- If no memory blackboxer is specified in the SpinalConfig, then the default one is added with "on request" policy
- Fix ResetArea

v0.11.4

- Add BitVector.resize(8 bits) syntax
- Remove BitVector.apply(Int,Int) in favor of BitVector.apply(Int downto Int)
- Vec.apply(UInt) is now emited with dedicated process + switch statement by backends instead of a 2->1 mux tree
- Verilog backend now use always@(*) instead of always@(a,b,c, ...)
- Rework BusSlaveFactory to allow multicycle registers access and to map memories
- restore onlyStdLogicVectorAtTopLevelIo feature
- Fix Vec(Vec(in/out/master/slave/Reg(x)))
- Others lib fixes

v0.11.3

- Now backends will automaticaly merge combinatorial process if they share some conditional scope
- Add xx.noBackendCombMerge feature to avoid the above feature on a specific signal
- BusSlaveFactory rework primitives to allow ranged access and bus halt request for multicycles registers
- remove automatic keywords from functions emited into the verilog backend
- Fix default feature when used on outputs
- More AXI4 fancy convertions functions
- Add noBackendCombMerge feature
- Add noCombLoopCheck syntax
- addGeneric syntax added for blackboxes
- Fix axi driveAx region default value
- Better quartus/vivado flow

v0.11.2

Allow to keep undrived all non-design-vital register

v0.11.1

Fix various issues due to the changes of the 0.11.1
- Fix clock signals pulling through components (sub component to toplevel)
- Fix noRegisterAsLatch phases. Also this phase is applied to all none vital signals, even if that wasn't specified, to be more user friendly.
- Fix cases when a clock is defined as an component output but is also  used in the same component to drive registers
- Better autoconnect <>  implementation with better error reports

v0.11.0

This version radicaly change how SpinalHDL compiler work without changing the SpinalHDL syntax itself.

New feature :
- inout and Analog signals
- InOutWrapper tools allow to generate toplevels with their TriStates io bundles  converted into native inout tristates

Improvments :
- Better error reporting
- Better VHDL/Verilog generation

More safety :
- Signal assignements  over writing is now considerated as an error (can be bypassed via xxx.allowOverride
- Register without data assignement are nos considerated as an error (can by bypassed via xxx.allowUnsetRegToAvoidLatch