Fix UartRx issue when the sampling window is set to 1

Fix Uart setSamplingRate to be more accurate

v0.10.13

- Fix support of BigInt in 'is' statments
- Fix verilog shift bitwidth
- Better sensitivity list in VHDL and Verilog when switch statments are emited
- fromGray is now compatible with Verilator
- Better FMax for AXI4 interconnect libraries

Fix BaseType generics

v0.10.11 -> verilog improvments

Time and frequancy DSL now return dedicated class instead of BigInt
Verilog backend is Verilator ready
Verilog backend support comment attributes on signal
Verilog backend now use the = assignement operator in combinatorial always blocks
Verilog backend now generate much less intermediate nodes for Bool and Bits stuffs
Verilog backend case detection is improved
Better error messaging
Component PrePopTask is now recusivly flushed

v0.10.10

- Fix corner case emition of clock domains when clocks are provided by BlackBox
- Better hierarchy violation reporting
- Better Modifier toString
- Add ResetCtrl.asyncAssertSyncDeassert
- Add ClockDomain.local
- refractoring of ActiveKind into Polarity

v0.10.9

- Alow the usage of the SpinalHDL compiler repository without having git in the PATH
- Add checks on enumeration encodings to detect overlappings
- Better name managment for enumeration encodings
- Add functional enumeration encoding factory
- Misc refractoring
- Catch null pointers exception and display an user friendly error message
- Fix StreamFifoCC reset states
- Better UartCtrlRx timings
- Add support of CTS generation in UartCtrl driveFrom.read

v0.10.8

- SpinalTags could now tell if they their host node could be symplified
- Autoconnect(<>) operator is now able to connect sliced bitvectors
- Add header in generated files
- More ScalaDoc
- More feature for Counter and Timeout tools
- Time and hertz DSL now return dedicated object (HertzNumber, TimeNumber)
- Fix BlackBoxULogic

v0.10.7

- fix corner cases dontCareNodes generation in backends
- refractor signals.unused into signals.allowPruning
- fix bugs that forget to add some sensitivity list elements in corner cases

v0.10.6

Add UF/SF literals functions for fixed point
Add fixed bitwidth shift for Bits/UInt/SInt (|<<   |>>)
Add edge function in Bool
Fixedpoint now use BigDecimal in place of Double
Better error reporting
Replace asBits/asUInt/asSInt(something) by B/U/S(something)