Smallfix for generated clock

sdc/Sdc.cc

@@ -1053,6 +1053,10 @@ void Sdc::createLibertyGeneratedClocks(Clock *clk) {
       Pin *pin = network_->findPin(pinName);
       if (pin && clkNetworkPins.hasKey(pin)) {
 
+        debugPrint(debug_, "libgenclk", 1, "Found generated clock pin %s "
+          "in liberty cell %s at path %s", 
+          pinName, cell->name(), network_->pathName(pin));
+
         // Search liberty cell for the corresponding generated clock
         for (const GeneratedClock *generatedClock : cell->generatedClocks()) {
 
@@ -1071,10 +1075,14 @@ void Sdc::createLibertyGeneratedClocks(Clock *clk) {
 
             // Hierarchical path of the generated clock pin
             // (name is with respect to source clock)
-            const char *generatedClockName = stringPrintTmp(
+            const char *generatedClockName = stringCopy(stringPrintTmp(
               "%s/%s", instPath,
               generatedClock->clockPin()
-            );
+            ));
+
+            debugPrint(debug_, "libgenclk", 1, "Creating generated clock %s "
+              "from clock %s in instance %s", 
+              generatedClockName, clk->name(), instPath);
 
             // Find the output pin, for nested generated clocks
             Pin *clkOutPin = network_->findPin(
@@ -1137,7 +1145,12 @@ Sdc::makeClock(const char *name,
   clearCycleAcctings();
   invalidateGeneratedClks();
   clkHpinDisablesInvalid();
-  createLibertyGeneratedClocks(clk);
+  if (network_->generatedClockPinsToCellMap().size() > 0) {
+    debugPrint(debug_, "libgenclk", 1, "Creating liberty-defined generated clocks "
+      "for clock %s by searching %lu liberty-defined generated clock pins", 
+      name, network_->generatedClockPinsToCellMap().size());
+    createLibertyGeneratedClocks(clk);
+  }
   return clk;
 }
 

verilog/VerilogReader.cc

@@ -1809,11 +1809,16 @@ VerilogReader::makeGeneratedClocks(LibertyCell *lib_cell, Instance *inst)
       }
 
       const char *masterPin = generated_clock->masterPin();
-      const char *pinPath = stringPrintTmp("%s/%s", inst_path, masterPin);
+      const char *pinPath =  stringCopy(stringPrintTmp("%s/%s",
+        inst_path, masterPin));
 
       // Map the full pinpath of source clock to the liberty cell
       // containing the generated clock definition
       network_->addGeneratedClockPinToCell(pinPath, lib_cell);
+
+      debugPrint(debug_, "libgenclk", 1, "Adding generated clock pin %s "
+        "to liberty cell %s for instance %s", 
+        pinPath, lib_cell->name(), inst_path);
     }
   }
 }