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cpu/sam3: reworked timer driver #4891

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merged 4 commits into from
Feb 27, 2016
Merged

cpu/sam3: reworked timer driver #4891

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6b9088a
cpu/sam3: changed timer vendor header
haukepetersen Feb 24, 2016
af5ba0b
cpu/sam3: reworked timer driver
haukepetersen Feb 24, 2016
39bff5d
boards/arduino-due: adjusted timer configuration
haukepetersen Feb 24, 2016
9787046
boards/udoo: adjusted timer configuration
haukepetersen Feb 24, 2016
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35 changes: 10 additions & 25 deletions boards/arduino-due/include/periph_conf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -38,31 +38,16 @@ extern "C" {
* @name Timer peripheral configuration
* @{
*/
#define TIMER_NUMOF (3U)
#define TIMER_0_EN 1
#define TIMER_1_EN 1
#define TIMER_2_EN 1

/* Timer 0 configuration */
#define TIMER_0_DEV TC0
#define TIMER_0_CHANNELS 6
#define TIMER_0_MAX_VALUE (0xffffffff)
#define TIMER_0_ISR1 isr_tc0
#define TIMER_0_ISR2 isr_tc1

/* Timer 1 configuration */
#define TIMER_1_DEV TC1
#define TIMER_1_CHANNELS 6
#define TIMER_1_MAX_VALUE (0xffffffff)
#define TIMER_1_ISR1 isr_tc3
#define TIMER_1_ISR2 isr_tc4

/* Timer 2 configuration */
#define TIMER_2_DEV TC2
#define TIMER_2_CHANNELS 6
#define TIMER_2_MAX_VALUE (0xffffffff)
#define TIMER_2_ISR1 isr_tc6
#define TIMER_2_ISR2 isr_tc7
static const timer_conf_t timer_config[] = {
/* dev, channel 0 ID */
{ TC0, ID_TC0 },
{ TC1, ID_TC3 },
};

#define TIMER_0_ISR isr_tc0
#define TIMER_1_ISR isr_tc3

#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
/** @} */

/**
Expand Down
31 changes: 8 additions & 23 deletions boards/udoo/include/periph_conf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -36,31 +36,16 @@ extern "C" {
* @name Timer peripheral configuration
* @{
*/
#define TIMER_NUMOF (3U)
#define TIMER_0_EN 1
#define TIMER_1_EN 1
#define TIMER_2_EN 1

/* Timer 0 configuration */
#define TIMER_0_DEV TC0
#define TIMER_0_CHANNELS 6
#define TIMER_0_MAX_VALUE (0xffffffff)
#define TIMER_0_ISR1 isr_tc0
#define TIMER_0_ISR2 isr_tc1
static const timer_conf_t timer_config[] = {
/* dev, channel 0 ID */
{ TC0, ID_TC0 },
{ TC1, ID_TC3 },
};

/* Timer 1 configuration */
#define TIMER_1_DEV TC1
#define TIMER_1_CHANNELS 6
#define TIMER_1_MAX_VALUE (0xffffffff)
#define TIMER_1_ISR1 isr_tc3
#define TIMER_1_ISR2 isr_tc4
#define TIMER_0_ISR isr_tc0
#define TIMER_1_ISR isr_tc3

/* Timer 2 configuration */
#define TIMER_2_DEV TC2
#define TIMER_2_CHANNELS 6
#define TIMER_2_MAX_VALUE (0xffffffff)
#define TIMER_2_ISR1 isr_tc6
#define TIMER_2_ISR2 isr_tc7
#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
/** @} */

/**
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18 changes: 18 additions & 0 deletions cpu/sam3/include/periph_cpu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -60,6 +60,16 @@ typedef uint32_t gpio_t;
*/
#define CPUID_LEN (16U)

/**
* @brief All SAM3 timers are 32-bit wide
*/
#define TIMER_MAX_VAL (0xffffffff)

/**
* @brief We use 3 channels for each defined timer
*/
#define TIMER_CHANNELS (3)

/**
* @brief Override values for pull register configuration
* @{
Expand Down Expand Up @@ -102,6 +112,14 @@ typedef enum {
GPIO_MUX_B = 1, /**< alternate function B */
} gpio_mux_t;

/**
* @brief Timer configuration data
*/
typedef struct {
Tc *dev; /**< timer device */
uint8_t id_ch0; /**< ID of the timer's first channel */
} timer_conf_t;

/**
* @brief UART configuration data
*/
Expand Down
4 changes: 1 addition & 3 deletions cpu/sam3/include/sam3x8e/component/component_tc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -49,9 +49,7 @@ typedef struct {
RwReg TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */
RoReg Reserved1[1];
RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */
RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */
RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */
RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */
RwReg TC_R[3]; /**< \brief (TcChannel Offset: 0x14) Register A-C */
RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */
RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
Expand Down
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