periph/spi: printing and testing SPI clock rates

tests/periph_spi: printing and testing SPI clock rates

drivers/periph_spi: change API of spi_acquire (from #15904)

drivers/periph_spi: add the `bus` parameter to spi_get_*()
This was necessary for implementations where multiple
devices can have different clock sources. This broke
the macros SPI_CLK_* that were reverted to an enum.

periph/spi: adapted to the new API
Arbitrary speed support was added to all implementations
where it was missing.

2023-06:
- rebased on current master
- some backports from 2022 #18374
- 3 new implementations adapted (gd32v, rpx0xx, and esp32)
- minial frequency asserts was replaced by return codes
- useless upper frequency bounding removed from many implementations
- SPI_DIV_UP was replaced by the new DIV_ROUND_UP from macros/math.h
- driver clock configuration caching was removed from implementations
  where it exists because it should be done at application level with
  this new API
- br computation was simplified for stm32 / gd32v as performace
  optimisation is no longer needed at this level and the inaccuracy
  of the fixed point arithmetic was unreliable for frequencies
  requested lower but close to resulting frequencies

.github/workflows/tools-buildtest.yml

@@ -28,8 +28,6 @@ jobs:
           path: dist/tools
         - name: bossa-nrf52
           path: dist/tools
-        - name: calc_spi_scalers
-          path: cpu/kinetis/dist
         - name: clk_conf
           path: cpu/stm32/dist
         - name: edbg

boards/common/kw41z/include/periph_conf_common.h

@@ -122,50 +122,6 @@ static const uart_conf_t uart_config[] = {
 #define LPUART_0_SRC        3
 /** @} */
 
-/**
- * @name   SPI clock configuration
- *
- * Clock configuration values based on the configured 16Mhz module clock.
- *
- * Auto-generated by:
- * cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c
- *
-* @{
-*/
-static const uint32_t spi_clk_config[] = {
-    (
-        SPI_CTAR_PBR(2) | SPI_CTAR_BR(5) |          /* -> 100000Hz */
-        SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(4) |
-        SPI_CTAR_PASC(2) | SPI_CTAR_ASC(4) |
-        SPI_CTAR_PDT(2) | SPI_CTAR_DT(4)
-    ),
-    (
-        SPI_CTAR_PBR(2) | SPI_CTAR_BR(3) |          /* -> 400000Hz */
-        SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(2) |
-        SPI_CTAR_PASC(2) | SPI_CTAR_ASC(2) |
-        SPI_CTAR_PDT(2) | SPI_CTAR_DT(2)
-    ),
-    (
-        SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) |          /* -> 1000000Hz */
-        SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(3) |
-        SPI_CTAR_PASC(0) | SPI_CTAR_ASC(3) |
-        SPI_CTAR_PDT(0) | SPI_CTAR_DT(3)
-    ),
-    (
-        SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) |          /* -> 4000000Hz */
-        SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(1) |
-        SPI_CTAR_PASC(0) | SPI_CTAR_ASC(1) |
-        SPI_CTAR_PDT(0) | SPI_CTAR_DT(1)
-    ),
-    (
-        SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) |          /* -> 4000000Hz */
-        SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(0) |
-        SPI_CTAR_PASC(0) | SPI_CTAR_ASC(0) |
-        SPI_CTAR_PDT(0) | SPI_CTAR_DT(0)
-    )
-};
-/** @} */
-
 /**
  * @name Random Number Generator configuration
  * @{

boards/frdm-k22f/include/periph_conf.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2017 Eistec AB
- *               2021-2023 Hugues Larrive
+ *               2023 Hugues Larrive
  *
  * This file is subject to the terms and conditions of the GNU Lesser General
  * Public License v2.1. See the file LICENSE in the top level directory for more
@@ -225,47 +225,8 @@ static const pwm_conf_t pwm_config[] = {
 
 /**
  * @name   SPI configuration
- *
- * Clock configuration values based on the configured 48Mhz module clock.
- *
- * Auto-generated by:
- * cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c
- *
-* @{
-*/
-static const uint32_t spi_clk_config[] = {
-    (
-        SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) |          /* -> 93750Hz */
-        SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
-        SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
-        SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
-    ),
-    (
-        SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) |          /* -> 375000Hz */
-        SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
-        SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
-        SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
-    ),
-    (
-        SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) |          /* -> 1000000Hz */
-        SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
-        SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
-        SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
-    ),
-    (
-        SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) |          /* -> 4800000Hz */
-        SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
-        SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
-        SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
-    ),
-    (
-        SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) |          /* -> 8000000Hz */
-        SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
-        SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
-        SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
-    )
-};
-
+ * @{
+ */
 static const spi_conf_t spi_config[] = {
     {
         .dev      = SPI0,

boards/frdm-k64f/include/periph_conf.h

@@ -252,47 +252,8 @@ static const pwm_conf_t pwm_config[] = {
 
 /**
  * @name   SPI configuration
- *
- * Clock configuration values based on the configured 30Mhz module clock.
- *
- * Auto-generated by:
- * cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c
- *
-* @{
-*/
-static const uint32_t spi_clk_config[] = {
-    (
-        SPI_CTAR_PBR(2) | SPI_CTAR_BR(6) |          /* -> 93750Hz */
-        SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(5) |
-        SPI_CTAR_PASC(2) | SPI_CTAR_ASC(5) |
-        SPI_CTAR_PDT(2) | SPI_CTAR_DT(5)
-    ),
-    (
-        SPI_CTAR_PBR(2) | SPI_CTAR_BR(4) |          /* -> 375000Hz */
-        SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(3) |
-        SPI_CTAR_PASC(2) | SPI_CTAR_ASC(3) |
-        SPI_CTAR_PDT(2) | SPI_CTAR_DT(3)
-    ),
-    (
-        SPI_CTAR_PBR(2) | SPI_CTAR_BR(2) |          /* -> 1000000Hz */
-        SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(4) |
-        SPI_CTAR_PASC(0) | SPI_CTAR_ASC(4) |
-        SPI_CTAR_PDT(0) | SPI_CTAR_DT(4)
-    ),
-    (
-        SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) |          /* -> 5000000Hz */
-        SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
-        SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
-        SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
-    ),
-    (
-        SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) |          /* -> 7500000Hz */
-        SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(1) |
-        SPI_CTAR_PASC(0) | SPI_CTAR_ASC(1) |
-        SPI_CTAR_PDT(0) | SPI_CTAR_DT(1)
-    )
-};
-
+ * @{
+ */
 static const spi_conf_t spi_config[] = {
     {
         .dev      = SPI0,

boards/mulle/include/periph_conf.h

@@ -260,47 +260,8 @@ static const pwm_conf_t pwm_config[] = {
 
 /**
  * @name SPI configuration
- *
- * Clock configuration values based on the configured 47988736Hz module clock.
- *
- * Auto-generated by:
- * cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c
- *
  * @{
  */
-static const uint32_t spi_clk_config[] = {
-    (
-        SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) |          /* -> 93728Hz */
-        SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
-        SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
-        SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
-    ),
-    (
-        SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) |          /* -> 374912Hz */
-        SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
-        SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
-        SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
-    ),
-    (
-        SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) |          /* -> 999765Hz */
-        SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
-        SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
-        SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
-    ),
-    (
-        SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) |          /* -> 4798873Hz */
-        SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
-        SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
-        SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
-    ),
-    (
-        SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) |          /* -> 7998122Hz */
-        SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
-        SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
-        SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
-    )
-};
-
 static const spi_conf_t spi_config[] = {
     {
         .dev      = SPI0,

boards/openlabs-kw41z-mini/include/periph_conf.h

@@ -267,47 +267,8 @@ static const pwm_conf_t pwm_config[] = {
 
 /**
  * @name   SPI configuration
- *
- * Clock configuration values based on the configured 16Mhz module clock.
- *
- * Auto-generated by:
- * cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c
- *
  * @{
  */
-static const uint32_t spi_clk_config[] = {
-    (
-        SPI_CTAR_PBR(2) | SPI_CTAR_BR(5) |          /* -> 100000Hz */
-        SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(4) |
-        SPI_CTAR_PASC(2) | SPI_CTAR_ASC(4) |
-        SPI_CTAR_PDT(2) | SPI_CTAR_DT(4)
-    ),
-    (
-        SPI_CTAR_PBR(2) | SPI_CTAR_BR(3) |          /* -> 400000Hz */
-        SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(2) |
-        SPI_CTAR_PASC(2) | SPI_CTAR_ASC(2) |
-        SPI_CTAR_PDT(2) | SPI_CTAR_DT(2)
-    ),
-    (
-        SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) |          /* -> 1000000Hz */
-        SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(3) |
-        SPI_CTAR_PASC(0) | SPI_CTAR_ASC(3) |
-        SPI_CTAR_PDT(0) | SPI_CTAR_DT(3)
-    ),
-    (
-        SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) |          /* -> 4000000Hz */
-        SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(1) |
-        SPI_CTAR_PASC(0) | SPI_CTAR_ASC(1) |
-        SPI_CTAR_PDT(0) | SPI_CTAR_DT(1)
-    ),
-    (
-        SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) |          /* -> 4000000Hz */
-        SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(0) |
-        SPI_CTAR_PASC(0) | SPI_CTAR_ASC(0) |
-        SPI_CTAR_PDT(0) | SPI_CTAR_DT(0)
-    )
-};
-
 static const spi_conf_t spi_config[] = {
     {
         .dev      = SPI0,

boards/pba-d-01-kw2x/include/periph_conf.h

@@ -174,47 +174,8 @@ static const pwm_conf_t pwm_config[] = {
 
 /**
  * @name    SPI device configuration
- *
- * Clock configuration values based on the configured 48Mhz module clock.
- *
- * Auto-generated by:
- * cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c
- *
  * @{
  */
-static const uint32_t spi_clk_config[] = {
-    (
-        SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) |          /* -> 93750Hz */
-        SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
-        SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
-        SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
-    ),
-    (
-        SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) |          /* -> 375000Hz */
-        SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
-        SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
-        SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
-    ),
-    (
-        SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) |          /* -> 1000000Hz */
-        SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
-        SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
-        SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
-    ),
-    (
-        SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) |          /* -> 4800000Hz */
-        SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
-        SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
-        SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
-    ),
-    (
-        SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) |          /* -> 8000000Hz */
-        SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
-        SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
-        SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
-    )
-};
-
 static const spi_conf_t spi_config[] = {
     {
         .dev      = SPI0,

cpu/atmega_common/include/periph_cpu_common.h

@@ -280,26 +280,14 @@ typedef enum {
 /** @} */
 
 /**
- * @brief   SPI speed selection macro
- *
- * We encode the speed in bits 2, 1, and 0, where bit0 and bit1 hold the SPCR
- * prescaler bits, while bit2 holds the SPI2X bit.
- */
-#define SPI_CLK_SEL(s2x, pr1, pr0)    ((s2x << 2) | (pr1 << 1) | pr0)
-
-/**
- * @name   Override SPI speed values
- *
- * We assume a master clock speed of 16MHz here.
+ * @brief   Override SPI clock configuration
  * @{
  */
 #define HAVE_SPI_CLK_T
-typedef enum {
-    SPI_CLK_100KHZ = SPI_CLK_SEL(0, 1, 1),      /**< 16/128 -> 125KHz */
-    SPI_CLK_400KHZ = SPI_CLK_SEL(1, 1, 0),      /**< 16/32  -> 500KHz */
-    SPI_CLK_1MHZ   = SPI_CLK_SEL(0, 0, 1),      /**< 16/16  -> 1MHz */
-    SPI_CLK_5MHZ   = SPI_CLK_SEL(0, 0, 0),      /**< 16/4   -> 4MHz */
-    SPI_CLK_10MHZ  = SPI_CLK_SEL(1, 0, 0)       /**< 16/2   -> 8MHz */
+typedef struct {
+    uint8_t spsr_spi2x;
+    uint8_t spcr_spr;
+    int err;
 } spi_clk_t;
 /** @} */
 #endif /* ifndef DOXYGEN */