fpga_diff: add fpga ci for vivado Integrated cabling resource testing #703
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Hierarchical utilization section not found. |
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Vivado Hierarchical utilization: section missing or extract failed. Please check the job logs for runme.log output. |
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Vivado Hierarchical utilization: section missing or extract failed. Please check the job logs for runme.log output. |
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Vivado Hierarchical utilization: section missing or extract failed. Please check the job logs for runme.log output. |
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Vivado Hierarchical utilization: ---- Hierarchical utilization (filtered, max depth: 4) ----
| Date : Wed Nov 12 15:00:12 2025
| Host : open01 running 64-bit Ubuntu 22.04.5 LTS
| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | URAM | DSP Blocks |
| fpga_top_debug | (top) | 204517 | 185858 | 14926 | 3733 | 170669 | 140 | 20 | 4 | 19 |
| (fpga_top_debug) | (top) | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| core_def | core_def | 204394 | 185735 | 14926 | 3733 | 170403 | 140 | 20 | 4 | 19 |
| (core_def) | core_def | 711 | 711 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| CFG_AXI_bridge_i | AXI_bridge | 3998 | 3591 | 296 | 111 | 5061 | 0 | 0 | 0 | 0 |
| (CFG_AXI_bridge_i) | AXI_bridge | 8 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| axi_apb_bridge_0 | AXI_bridge_axi_apb_bridge_0_0 | 85 | 85 | 0 | 0 | 142 | 0 | 0 | 0 | 0 |
| axi_interconnect_0 | AXI_bridge_axi_interconnect_0_0 | 3538 | 3150 | 296 | 92 | 4610 | 0 | 0 | 0 | 0 |
| axi_uart16550_0 | AXI_bridge_axi_uart16550_0_0 | 367 | 348 | 0 | 19 | 309 | 0 | 0 | 0 | 0 |
| RTC_CLK_CTRL | fpga_clock_gate | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| SOC_CLK_CTRL | fpga_clock_gate_0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| U_CPU_TOP | SimTop_wrapper | 113409 | 104097 | 9312 | 0 | 71703 | 17 | 13 | 4 | 16 |
| (U_CPU_TOP) | SimTop_wrapper | 121 | 121 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_SimTop | SimTop | 113288 | 103976 | 9312 | 0 | 71703 | 17 | 13 | 4 | 16 |
| U_JTAG_DDR_SUBSYS | jtag_ddr_subsys_wrapper | 25640 | 21383 | 2680 | 1577 | 34281 | 46 | 7 | 0 | 3 |
| (U_JTAG_DDR_SUBSYS) | jtag_ddr_subsys_wrapper | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| jtag_ddr_subsys_i | jtag_ddr_subsys | 25640 | 21383 | 2680 | 1577 | 34281 | 46 | 7 | 0 | 3 |
| U_SYS_CFG | syscfg | 4 | 4 | 0 | 0 | 9 | 0 | 0 | 0 | 0 |
| data_bridge_i | data_bridge | 2920 | 2760 | 0 | 160 | 4093 | 0 | 0 | 0 | 0 |
| (data_bridge_i) | data_bridge | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| axi_interconnect_0 | data_bridge_axi_interconnect_0_0 | 2920 | 2760 | 0 | 160 | 4093 | 0 | 0 | 0 | 0 |
| u_rom | blk_mem_gen_0 | 134 | 134 | 0 | 0 | 70 | 1 | 0 | 0 | 0 |
| (u_rom) | blk_mem_gen_0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| U0 | blk_mem_gen_v8_4_4 | 134 | 134 | 0 | 0 | 70 | 1 | 0 | 0 | 0 |
| u_xdma_axi4lite_bar | XDMA_AXI4LiteBar | 109 | 109 | 0 | 0 | 332 | 0 | 0 | 0 | 0 |
| xdma_ep_i | xdma_ep | 57467 | 52944 | 2638 | 1885 | 54841 | 76 | 0 | 0 | 0 |
| (xdma_ep_i) | xdma_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| axi_interconnect_0 | xdma_ep_axi_interconnect_0_0 | 54 | 54 | 0 | 0 | 372 | 0 | 0 | 0 | 0 |
| axis_interconnect_0 | xdma_ep_axis_interconnect_0_0 | 723 | 387 | 336 | 0 | 2457 | 0 | 0 | 0 | 0 |
| util_ds_buf_0 | xdma_ep_util_ds_buf_0_0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| xdma_0 | xdma_ep_xdma_0_0 | 56690 | 52503 | 2302 | 1885 | 52012 | 76 | 0 | 0 | 0 |
| xilnx_crg | xilnx_crg | 1 | 1 | 0 | 0 | 13 | 0 | 0 | 0 | 0 |
| devclk_rstn | RST_SYNC | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 0 |
| pclk_slow_rstn | RST_SYNC_1 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 0 |
| sysclk_rstn | RST_SYNC_2 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | 0 |
| tmclk_rstn | RST_SYNC_3 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 0 |
| dbg_hub | dbg_hub_CV | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_cpu_rstn | button_debounce | 16 | 16 | 0 | 0 | 28 | 0 | 0 | 0 | 0 |
| u_vio | vio_0 | 102 | 102 | 0 | 0 | 237 | 0 | 0 | 0 | 0 |
| (u_vio) | vio_0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| inst | vio_0_vio_v3_0_19_vio | 102 | 102 | 0 | 0 | 237 | 0 | 0 | 0 | 0 |
| (inst) | vio_0_vio_v3_0_19_vio | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 |
| DECODER_INST | vio_0_vio_v3_0_19_decoder | 13 | 13 | 0 | 0 | 48 | 0 | 0 | 0 | 0 |
| PROBE_OUT_ALL_INST | vio_0_vio_v3_0_19_probe_out_all | 12 | 12 | 0 | 0 | 12 | 0 | 0 | 0 | 0 |
| U_XSDB_SLAVE | vio_0_xsdbs_v1_0_2_xsdbs | 77 | 77 | 0 | 0 | 161 | 0 | 0 | 0 | 0 | |
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Current result (nutshell) - 2025-11-12 17:16
Archive: no previous record found (first run or less than one day) |
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Current result (nutshell) - 2025-11-13 11:46
Archive: no previous record found (first run or less than one day) |
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Current result (nutshell) - 2025-11-26 17:25
Archive (latest, 20251113)
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Current result (nutshell) - 2025-11-27 17:49
Archive (latest, 20251126)
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Current result (nutshell) - 2025-12-02 11:31
Archive (latest, 20251127)
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Current result (nutshell) - 2025-12-02 12:18
Archive (latest, 20251127)
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