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fpga_diff: add fpga ci for vivado Integrated cabling resource testing
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‎.github/workflows/evening.yml‎

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name: Evening Regression
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on:
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schedule:
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# 12:00 UTC == 20:00 UTC+8
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- cron: '00 12 * * *'
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# Delete after the PR test is passed.
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pull_request:
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types: [opened, synchronize, reopened, ready_for_review]
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jobs:
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test-fpga-nutshell:
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if: ${{ github.event_name == 'pull_request' }}
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timeout-minutes: 1440
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runs-on: self-hosted
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steps:
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- uses: actions/checkout@v4
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- name: Prepare NutShell
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run: |
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cd $GITHUB_WORKSPACE/..
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rm -rf NutShell && rm -rf env-scripts
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proxychains git clone -b dev-difftest --single-branch --depth 1 https://github.com/OSCPU/NutShell.git
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cd NutShell && make init && rm -rf difftest && cp -r $GITHUB_WORKSPACE .
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echo "NOOP_HOME=$(pwd)" >> $GITHUB_ENV
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echo "DUT_HOME=$(pwd)/build" >> $GITHUB_ENV
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echo "DIFFTEST_LOG=/nfs/home/ci-runner/ci-runner-difftest/pr_log" >> "$GITHUB_ENV"
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echo "/nfs/home/tools/Xilinx/Vivado/2020.2/bin" >> "$GITHUB_PATH"
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- name: Prepare FPGA scripts
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run: |
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cd $GITHUB_WORKSPACE/..
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proxychains git clone -b dev_difftest --single-branch --depth 1 https://github.com/OpenXiangShan/env-scripts.git
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cd env-scripts
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echo "ENV_SCRIPTS_HOME=$(pwd)" >> $GITHUB_ENV
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- name: Build NutShell
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run: |
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cd $NOOP_HOME
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make verilog BOARD=fpgadiff MILL_ARGS="--difftest-config ESBIF" -j2
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cp -i ./difftest/src/test/vsrc/fpga/fpga_clock_gate.v ./build/rtl/
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- name: Create FPGA project
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run: |
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source /nfs/home/tools/Xilinx/Vivado/2020.2/settings64.sh
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cd $GITHUB_WORKSPACE/../env-scripts/fpga_diff
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make update_core_flist CORE_DIR=$DUT_HOME
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make vivado CPU=nutshell
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- name: Build FPGA synth
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run: |
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source /nfs/home/tools/Xilinx/Vivado/2020.2/settings64.sh
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cd $ENV_SCRIPTS_HOME/fpga_diff
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make synth PRJ=./fpga_nutshell/fpga_nutshell.xpr
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bash ./tools/generate_reports.sh nutshell
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- name: Extract Vivado Hierarchical utilization
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run: |
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set -euo pipefail
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IN_PATH=$ENV_SCRIPTS_HOME/fpga_diff
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MD_PATH="$RUNNER_TEMP/vivado_hier_filtered.md"
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python3 $NOOP_HOME/difftest/scripts/fpga/ci.py --input "$IN_PATH" --cpu nutshell \
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--filter-instance-root U_CPU_TOP --filter-modules HostEndpoint,GatewayEndpoint,nutcore \
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--csv-md-output "$MD_PATH"
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echo "VIVADO_HIER_MD=$MD_PATH" >> "$GITHUB_ENV"
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- name: Comment utilization to PR
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if: ${{ github.event_name == 'pull_request' }}
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uses: actions/github-script@v7
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env:
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VIVADO_HIER_MD: ${{ env.VIVADO_HIER_MD }}
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with:
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script: |
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const fs = require('fs');
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let body;
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try {
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body = fs.readFileSync(process.env.VIVADO_HIER_MD, 'utf8');
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if (!body.trim()) throw new Error('empty');
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} catch (e) {
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body = 'Vivado Hierarchical utilization: section missing or extract failed. Please check the job logs for runme.log output.';
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}
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await github.rest.issues.createComment({ owner: context.repo.owner, repo: context.repo.repo, issue_number: context.issue.number, body });
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test-fpga-xiangshan-miniconfig:
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if: ${{ github.event_name == 'schedule' }}
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timeout-minutes: 1440
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runs-on: self-hosted
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steps:
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- uses: actions/checkout@v4
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- name: Prepare XiangShan
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run: |
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cd $GITHUB_WORKSPACE/..
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rm -rf XiangShan && rm -rf env-scripts
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proxychains git clone --depth 1 https://github.com/OpenXiangShan/XiangShan.git
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cd XiangShan && make init && rm -rf difftest && cp -r $GITHUB_WORKSPACE .
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echo "NOOP_HOME=$(pwd)" >> $GITHUB_ENV
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echo "DIFF_HOME=$NOOP_HOME/difftest/nightly_log" >> $GITHUB_ENV
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echo "DUT_HOME=$(pwd)/build" >> $GITHUB_ENV
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echo "DIFFTEST_LOG=/nfs/home/ci-runner/ci-runner-difftest/evening_log" >> "$GITHUB_ENV"
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- name: Prepare FPGA scripts
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run: |
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cd $GITHUB_WORKSPACE/..
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proxychains git clone --depth 1 https://github.com/OpenXiangShan/env-scripts.git
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cd env-scripts
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echo "ENV_SCRIPTS_HOME=$(pwd)" >> $GITHUB_ENV
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- name: Build Xiangshan
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run: |
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cd $NOOP_HOME
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make verilog FPGA_DIFF=1 CONFIG=FpgaDiffDefaultConfig PLDM_ARGS="--difftest-config ESBIFDU --difftest-exclude Vec" PLDM=1 WITH_CHISELDB=0 WITH_CONSTANTIN=0
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cp -r $DIFF_HOME/src/test/vsrc/fpga $DUT_HOME
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- name: Create FPGA project
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run: |
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PATH=$PATH:/nfs/home/tools/Xilinx/Vivado/2020.2/bin
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source /nfs/home/tools/Xilinx/Vivado/2020.2/settings64.sh
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cd $GITHUB_WORKSPACE/../env-scripts/fpga_diff
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make update_core_flist CORE_DIR=$DUT_HOME
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make vivado CPU=xiangshan
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- name: Build FPGA synth
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run: |
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cd $GITHUB_WORKSPACE/../env-scripts/fpga_diff
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make synth PRJ=fpga_xiangshan/fpga_xiangshan.xpr
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bash ./tools/generate_reports.sh xiangshan
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- name: Print Vivado Hierarchical utilization to logs
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run: |
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set -euo pipefail
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IN_PATH=$ENV_SCRIPTS_HOME/fpga_diff
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echo "===== Vivado Hierarchical utilization ====="
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MD_PATH="$RUNNER_TEMP/vivado_hier_filtered_xs.md"
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python3 "$GITHUB_WORKSPACE/scripts/fpga/ci.py" --input "$IN_PATH" --cpu xiangshan \
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--filter-instance-root U_CPU_TOP --filter-modules HostEndpoint,GatewayEndpoint,XSTop \
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--csv-md-output "$MD_PATH" --format text
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cat "$MD_PATH"" >> "$GITHUB_STEP_SUMMARY"
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- name: Publish artifacts
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uses: actions/upload-artifact@v4
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with:
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name: xiangshan-vivado-hier-${{ github.run_id }}
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path: ${{ runner.temp }}/xiangshan_artifacts

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