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Fix bugs (#28)
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* miscs: fix prefetcher missing connection after removing DontCare

* miscs: fix useless assignment

* miscs: fix gotGrantData not initialized

* miscs: fix typo

* miscs: fix l1_pf connection

* miscs: fix sourceC missing reqSource
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Ivyfeather authored Jul 25, 2023
1 parent a59c242 commit 653025f
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Showing 5 changed files with 8 additions and 2 deletions.
2 changes: 1 addition & 1 deletion src/main/scala/coupledL2/Directory.scala
Original file line number Diff line number Diff line change
Expand Up @@ -258,7 +258,7 @@ class Directory(implicit p: Parameters) extends L2Module {
dontTouch(metaArray.io)
dontTouch(tagArray.io)

io.read.ready := !io.metaWReq.valid && !io.tagWReq.valid && !replacerWen
// io.read.ready := !io.metaWReq.valid && !io.tagWReq.valid && !replacerWen
val replacerRready = if(cacheParams.replacement == "random") true.B else replacer_sram_opt.get.io.r.req.ready
io.read.ready := tagArray.io.r.req.ready && metaArray.io.r.req.ready && replacerRready

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1 change: 1 addition & 0 deletions src/main/scala/coupledL2/MSHR.scala
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Expand Up @@ -96,6 +96,7 @@ class MSHR(implicit p: Parameters) extends L2Module {
req.reqSource := msTask.reqSource
gotT := false.B
gotDirty := false.B
gotGrantData := false.B
probeDirty := false.B
probeGotN := false.B
timer := 1.U
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2 changes: 1 addition & 1 deletion src/main/scala/coupledL2/MainPipe.scala
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Expand Up @@ -397,7 +397,7 @@ class MainPipe(implicit p: Parameters) extends L2Module {
io.nestedwb.set := req_s3.set
io.nestedwb.tag := req_s3.tag
io.nestedwb.b_toN := task_s3.valid && metaW_valid_s3_b && req_s3.param === toN
io.nestedwb.b_toB := task_s3.valid && metaW_valid_s3_b && req_s3.param =/= toB // assume L3 won't send Probe toT
io.nestedwb.b_toB := task_s3.valid && metaW_valid_s3_b && req_s3.param === toB // assume L3 won't send Probe toT
io.nestedwb.b_clr_dirty := task_s3.valid && metaW_valid_s3_b && meta_s3.dirty
// c_set_dirty is true iff Release has Data
io.nestedwb.c_set_dirty := task_s3.valid && metaW_valid_s3_c && wen_c
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1 change: 1 addition & 0 deletions src/main/scala/coupledL2/SourceC.scala
Original file line number Diff line number Diff line change
Expand Up @@ -139,6 +139,7 @@ class SourceC(implicit p: Parameters) extends L2Module {
c.address := Cat(task.tag, task.set, task.off)
c.data := data
c.corrupt := false.B
c.user.lift(utility.ReqSourceKey).foreach(_ := task.reqSource)
c.echo.lift(DirtyKey).foreach(_ := task.dirty)
c
}
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4 changes: 4 additions & 0 deletions src/main/scala/coupledL2/prefetch/Prefetcher.scala
Original file line number Diff line number Diff line change
Expand Up @@ -129,6 +129,10 @@ class Prefetcher(implicit p: Parameters) extends PrefetchModule {
val bop_en = RegNextN(io_l2_pf_en, 2, Some(true.B))
// l1 prefetch
l1_pf.io.recv_addr := ValidIODelay(io.recv_addr, 2)
l1_pf.io.train.valid := false.B
l1_pf.io.train.bits := 0.U.asTypeOf(new PrefetchTrain)
l1_pf.io.resp.valid := false.B
l1_pf.io.resp.bits := 0.U.asTypeOf(new PrefetchResp)
// l2 prefetch
bop.io.train <> io.train
bop.io.resp <> io.resp
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